Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37803 )
Change subject: chipset_enable.c: Mark Intel HM76 as DEP ......................................................................
chipset_enable.c: Mark Intel HM76 as DEP
Tested reading, writing and erasing the internal flash chip using a Samsung NP530U3C laptop with an Intel HM76 PCH. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well.
Change-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/37803/1
diff --git a/chipset_enable.c b/chipset_enable.c index b55852c..e826d90 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1831,7 +1831,7 @@ {0x8086, 0x1e56, B_FS, DEP, "Intel", "QS77", enable_flash_pch7}, {0x8086, 0x1e57, B_FS, DEP, "Intel", "HM77", enable_flash_pch7}, {0x8086, 0x1e58, B_FS, NT, "Intel", "UM77", enable_flash_pch7}, - {0x8086, 0x1e59, B_FS, NT, "Intel", "HM76", enable_flash_pch7}, + {0x8086, 0x1e59, B_FS, DEP, "Intel", "HM76", enable_flash_pch7}, {0x8086, 0x1e5d, B_FS, NT, "Intel", "HM75", enable_flash_pch7}, {0x8086, 0x1e5e, B_FS, NT, "Intel", "HM70", enable_flash_pch7}, {0x8086, 0x1e5f, B_FS, DEP, "Intel", "NM70", enable_flash_pch7},
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/37803 )
Change subject: chipset_enable.c: Mark Intel HM76 as DEP ......................................................................
Patch Set 1: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/37803 )
Change subject: chipset_enable.c: Mark Intel HM76 as DEP ......................................................................
chipset_enable.c: Mark Intel HM76 as DEP
Tested reading, writing and erasing the internal flash chip using a Samsung NP530U3C laptop with an Intel HM76 PCH. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well.
Change-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/37803 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Edward O'Callaghan quasisec@chromium.org --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved
diff --git a/chipset_enable.c b/chipset_enable.c index b55852c..e826d90 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1831,7 +1831,7 @@ {0x8086, 0x1e56, B_FS, DEP, "Intel", "QS77", enable_flash_pch7}, {0x8086, 0x1e57, B_FS, DEP, "Intel", "HM77", enable_flash_pch7}, {0x8086, 0x1e58, B_FS, NT, "Intel", "UM77", enable_flash_pch7}, - {0x8086, 0x1e59, B_FS, NT, "Intel", "HM76", enable_flash_pch7}, + {0x8086, 0x1e59, B_FS, DEP, "Intel", "HM76", enable_flash_pch7}, {0x8086, 0x1e5d, B_FS, NT, "Intel", "HM75", enable_flash_pch7}, {0x8086, 0x1e5e, B_FS, NT, "Intel", "HM70", enable_flash_pch7}, {0x8086, 0x1e5f, B_FS, DEP, "Intel", "NM70", enable_flash_pch7},
-
Angel Pons (Code Review) -
Edward O'Callaghan (Code Review)
-
Nico Huber (Code Review)