flashrom August 2010

flashrom@flashrom.org

77 participants
209 discussions

Flashrom Issues
by Johnson, Je 10 Aug '10

10 Aug '10

I've been working with a Supermicro X8DA3/DAI mother board running with RHEL ES 5.4 (2.6.30.9). I compiled the latest version of "flashrom 0.9.2) and was able to capture my current BIOS by running "flashrom -r X8DA3.BIOS". After capturing the BIOS I reloaded it by issuing the following command "flashrom -w X8DA3.BIOS". I was told that the write was successful, but saw the following errors: Writing flash chip... Erasing flash before programming Erasing Flash Chip... spi_block_erase_20 failed during command execution at address 0x0 Spi_block_erase_52 failed during command execution at address 0x0 Since it stated that it was successfully, I simply reset the server and now it's failing to boot? Any help in understanding in what went wrong or if my motherboard is not fully support ( I did run the check initially to ensure the chipset was support). Thanks, John Johnson Lockheed Martin Manassas, VA

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[PATCH][superiotool] ITE IT8500 EC support
by Donald.Huang＠ite.com.tw 10 Aug '10

10 Aug '10

The attached patch adds a register table for the IT8500 embedded controller. Here is a sample of the output: superiotool r5679 Found ITE IT8500 (id=0x8500, rev=0x1) at 0x2e Register dump: idx 20 21 22 23 25 2d 2e 2f 30 val 85 00 01 01 00 00 00 00 01 def 85 00 01 01 00 00 NA NA 00 LDN 0x04 (System Wake-Up Control (SWUC)) idx 30 60 61 62 63 70 71 val 01 00 00 00 00 00 01 def 00 00 00 00 00 00 01 LDN 0x05 (KBC/Mouse Interface) idx 30 60 61 62 63 70 71 val 01 00 00 00 00 0c 01 def 00 00 00 00 00 0c 01 LDN 0x06 (KBC/Keyboard Interface) idx 30 60 61 62 63 70 71 val 01 00 60 00 64 01 01 def 00 00 60 00 64 01 01 LDN 0x0f (Shared Memory/Flash Interface (SMFI)) idx 30 60 61 62 63 70 71 f4 val 01 02 00 00 00 00 00 09 def 00 00 00 00 00 00 00 NA LDN 0x10 (BRAM) idx 30 62 63 70 71 f3 f4 f5 val 01 05 00 08 01 00 3f 3f def 00 00 72 08 01 NA NA NA LDN 0x11 (Power Management I/F Channel 1 (PMC1)) idx 30 60 61 62 63 70 71 val 01 00 62 00 66 00 01 def 00 00 62 00 66 01 01 LDN 0x12 (Power Management I/F Channel 2 (PMC2)) idx 30 60 61 62 63 64 65 70 71 f0 val 01 00 80 00 84 04 00 02 01 00 def 00 00 68 00 6c 00 00 01 01 NA Found SMSC SCH5317 (id=0x85, rev=0x00) at 0x2e No dump available for this Super I/O Signed-off by: Donald Huang (donald.huang(a)ite.com.tw) Signed-off by: Yung-chieh Lo (yjlou(a)google.com) Signed-off by: David Hendricks (dhendrix(a)google.com)

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ASUS A8N/A8N-SLI Deluxe clarification (was: Re: erase failed on ASUS A8N-SLI Deluxe.)
by Uwe Hermann 09 Aug '10

09 Aug '10

Hi, On Tue, Dec 15, 2009 at 03:39:49PM +0100, Luc Verhaegen wrote: > On Fri, Nov 06, 2009 at 03:40:20PM +0100, Andreas Henriksson wrote: > > Hello everybody! > > > > I've been unsuccessful in updating by BIOS on my ASUS A8N-SLI Deluxe > > motherboard using flashrom. To my novice eyes it looks like the first > > 768kB has been erased and the rest left as is.... > > > > I'll put some information below.... > > > > Although i think that this will be more a flashchip issue than > anything else, please give this patch a whirl. > > Luc Verhaegen. > >From 1279b579a377a638c7f9045519a1b9e0e8497828 Mon Sep 17 00:00:00 2001 > From: Luc Verhaegen <libv(a)skynet.be> > Date: Tue, 15 Dec 2009 15:28:18 +0100 > Subject: [PATCH] Board: Add Asus A8N. > > Signed-off-by: Luc Verhaegen <libv(a)skynet.be> > --- > board_enable.c | 1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/board_enable.c b/board_enable.c > index 19a77e9..f8b1e10 100644 > --- a/board_enable.c > +++ b/board_enable.c > @@ -1128,6 +1128,7 @@ struct board_pciid_enable board_pciid_enables[] = { > {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x}, > {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, > {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", w836xx_memw_enable_2e}, > + {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, "ASUS", "A8N", board_shuttle_fn25}, Hi, this patch was comitted as r949. We currently mark the board-enable as untested. Andreas, can you please try if the latest flashrom version from svn trunk detects your board correctly and (more importantly) if writing/erasing the chip in that board works OK? Also, which board exactly do you have, the "ASUS A8N-SLI Deluxe" or "ASUS A8N"? If the first, we need to fix the name in our code. The A8N seems to be a laptop also, see: http://www.asus.com/product.aspx?P_ID=piUw2tNdosMjBF36 Please post the following output if possible: * flashrom -V * lspci -nnvvvxxx (as root) * superiotool -deV If you can recover please also post the output of a write or erase operation (using the latest flashrom from svn). Thanks, Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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Re: [flashrom] New Intel Chipsets
by Michael Karcher 09 Aug '10

09 Aug '10

Am Montag, den 09.08.2010, 09:55 +0200 schrieb Wagner, Helge (GE Intelligent Platforms): > Hi Michael, > > >This patch has one minor issue: flash_enable_ich_dc_spi decodes the > BIOS type select straps. > > The function is called "enable_flash_ich_dc_spi" (for those that try to > find it in the source). > > In this function the BIOS type select strap is not honored at all except > for ICH7: > ... > if (ich_generation == 7) { > if(bbs == ICH_STRAP_LPC) { > /* No further SPI initialization required */ > return ret; > } > else > /* Disable LPC/FWH if strapped to PCI or SPI */ > buses_supported = 0; > } > ... > So it should all be ok already for new chipsets. Do you agree? The state it is now (that the bbs is ignored for newer chipsets) is becasue we were already aware of the problem. Still the debugging print in the beginning is wrong, especially for 5 Series/3400 series. I'm going to commit your patch as it does not break anything, and adds working support for the new chipsets. We are checking bbs for ICH7 because that chipset supports *either* LPC/FWH *or* the SPI interface and never both interfaces run at the same time. This is different for later chipsets where the SPI chip can be addressed through the software sequencing registers even if the system boots from LPC flash. Regards, Michael Karcher

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Re: [flashrom] Blank check
by Wagner, Helge (GE Intelligent Platforms) 09 Aug '10

09 Aug '10

>There is at least one (old crappy) chip that needs also the 0xff bytes. Which flash chip(s) are affected? Maybe there should be an additional field named "requires_full_programming" in the "struct flashchip". And/or there should be a command line option to switch full programming on/off (depending on the default state). Regards, Helge -----Original Message----- From: Reinder de Haan [mailto:rs@mveas.com] Sent: Samstag, 7. August 2010 01:16 To: Wagner, Helge (GE Intelligent Platforms) Subject: Re: [flashrom] Blank check Just a note : There is at least one (old crappy) chip that needs also the 0xff bytes.. afaik flashrom already skips 0xff (atleast the jedec write does iirc) greetings, Reinder Wagner, Helge (GE Intelligent Platforms) wrote: > I am not sure if this was discussed before, but i would suggest to > skip programming blocks/areas which should be programmed to the erased state. > E.g. if half of the input file consists of 0xFF areas, we could half > the programming time. > > And on chips where read is much faster than erase (e.g. SST 25VF...) > we can speed up erasing if we do a read before erase and only erase > that blocks that are not already in the erased state. > > Regards, > Helge > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

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[PATCH] Initial ITE IT8500 EC support
by Donald.Huang＠ite.com.tw 09 Aug '10

09 Aug '10

The attached patch adds generalized support for IT8500/IT8502 embedded controllers. The patch was developed by Google for Flashrom r1082, but applies cleanly against r1130. It was tested for IT8500E on a Chrome OS platform and may require modification depending on ODM/OEM customization and EC firmware version. This patch is not officially supported by ITE Tech Inc. Signed-off by: Donald Huang (donald.huang(a)ite.com.tw) Signed-off by: Yung-chieh Lo (yjlou(a)google.com) Signed-off by: David Hendricks (dhendrix(a)google.com)

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[PATCH 05/11] Rebased Board Enable Patch: A8JM board_enable patch (was Re: A8JM flashrom unable to erase)
by Sean Nelson 09 Aug '10

09 Aug '10

This patch replaces the earlier one sent, and adds A8JM (and possibly all A8J series) support, and additionally adds DMI detection of A8J, after the r896 fix to dmi detection. Signed-off-by: James Lancaster <deathstalker(a)gmail.com> The DMI identification triggers on either the 2nd or 5th dmi strings, which are both "A8J" followed by different numbers of spaces. Combined with the PCI IDs, it might work on any of the A8J series seeing that the main difference in all but the A8JS is the video card/screen (possibly that too, while there they did add sata in place of IDE). I believe (based on having a video card that was supposed to only be on the A8JS, that it has a different device number (1232), that the A8JS will not be picked up.) I've tested this on my own computer, it picks it up and appears to flash just fine. I think I probably should have added Acked by as it works, but I'll be conservative on the issue. --- board_enable.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 36bf6e4..89dad8a 100644 --- a/board_enable.c +++ b/board_enable.c @@ -910,26 +910,34 @@ static int intel_ich_gpio_set(int gpio, int raise) return 0; } /** * Suited for Abit IP35: Intel P35 + ICH9R. * Suited for Abit IP35 Pro: Intel P35 + ICH9R. */ static int intel_ich_gpio16_raise(const char *name) { return intel_ich_gpio_set(16, 1); } /** + * Suited for ASUS A8JM: Intel 945 + ICH7 + */ +static int intel_ich_gpio34_raise(const char *name) +{ + return intel_ich_gpio_set(34, 1); +} + +/** * Suited for MSI MS-7046: LGA775 + 915P + ICH6. */ static int intel_ich_gpio19_raise(const char *name) { return intel_ich_gpio_set(19, 1); } /** * Suited for: * - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. * - Asus P4C800-E Deluxe: socket478 + 875P + ICH5. * - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. */ @@ -1290,26 +1298,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, NT, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, + {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, NULL, "Biostar", "P4M80-M4", 0, OK, it8705f_write_enable_2e}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e}, @@ -1323,27 +1332,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, NULL, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", 0, OK, it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, NULL, "GIGABYTE", "GA-M61P-S3", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x7910, 0x1458, 0x5000, 0x1002, 0x438D, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-MA69VM-S2", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", 0, OK, it87xx_probe_spi_flash}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, - {0x8086, 0x27A0, 0, 0, 0x8086, 0x27b8, 0, 0, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, + {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, board_soyo_sy_7vca}, -- 1.6.6

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[PATCH] Board enable for ASUS A8N-LA (HP NAGAMI)
by Sean Nelson 08 Aug '10

08 Aug '10

Reversed-engineered board enable for the ASUS A8N-LA. IDs are ISA and SMBus. Added dmi string to match 3 HP boards: Nagami, Nagami2, Nagami2L. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

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[PATCH] Board enable for Asus P4S800-MX
by David Borg 08 Aug '10

08 Aug '10

Tested and works. Thanks to Carl-Daniel Hailfinger for simplifying the chipset enable for this board! Index: board_enable.c =================================================================== --- board_enable.c (revision 1127) +++ board_enable.c (working copy) @@ -352,7 +352,9 @@ } /** - * w83627: Enable MEMW# and set ROM size to max. + * Enable MEMW# and set ROM size to max. + * Supported chips: + * W83L517D, W83697HF/F/HG, W83697SF/UF/UG */ static void w836xx_memw_enable(uint16_t port) { @@ -1715,6 +1717,7 @@ {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, + {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x0003, 0, 0, "^P4S800-MX$", NULL, NULL, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, Signed-off-by: David Borg <borg.db(a)gmail.com> On 28 July 2010 03:06, David Borg <borg.db(a)gmail.com> wrote: > > Updated the patch to remove anything related to chip (un)locking, as there is no way to unlock the superio except by a cold reset. > > Logs for the different flashrom runs and the outputs of lspci -nnvvvxxx and superiotool -deV are also attached. > > w836xx_memw_enable will work for this board, however i'd still like to see the function corrected for completeness sake. I haven't yet found a datasheet for a superio in the w83627 family where the function is correct, and the supported superio's all work with sio_mask(port, 0x24, 0x28, 0x38); Perhaps it should be fixed in a separate patch? > > Regards, > David > > On 1 July 2010 11:50, David Borg <borg.db(a)gmail.com> wrote: >> >> Patch to add support for the Asus P4S800-MX motherboard and SIS 963 >> chipset. Invalidates previous patch: [PATCH] add support for SIS963 >> >> If anyone has the output of superiotool -deV for the following working >> boards, please forward them, so I can merge the functions >> w836xx_unlock_memw_enable_2e and w836xx_memw_enable_2e, and maybe fix >> the function w836xx_memw_enable which I believe has a typo, such that >> sio_mask(port, 0x24, 0x28, 0x28); >> becomes : sio_mask(port, 0x24, 0x28, 0x38); >> >> Motherboards: >> Albatron - PM266A Pro >> ASUS - A7V8X-MX SE >> EPoX - EP-8K5A2 >> Shuttle - AK31 >> Tyan - S2498 (Tomcat K7M) >> Termtek - TK-3370 (Rev:2.5B) >> MSI - MS-6590 (KT4 Ultra) >> MSI - MS-6712 (KT4V) >> MSI - MS-7005 (651M-L) >> >> Signed-off-by: David Borg <borg.db(a)gmail.com> >> >> Regards, >> David > > > > -- > David Borg -- David Borg

4 9

Re: [flashrom] [PATCH] Add dmidecode quirk workaround
by Michael Karcher 08 Aug '10

08 Aug '10

[I put the list back into Cc:] Am Sonntag, den 08.08.2010, 11:06 -0700 schrieb Sean Nelson: > > Upcoming Fedora 14 doesn't have this problem, but the patch doesn't > > hurt either. So, this is > > Acked-by: Sean Nelson <audiohacked(a)gmail.com> > I should clearify my previous message in that MY fedora system doesn't > show the problem. If you don't have the problem, most likely your SMBIOS does not declare a version number above 2.6. I clarified the comment to state the fact. No problem, thanks for the Ack. committed in r1136. Regards, Michael Karcher

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flashrom August 2010