External programmers
by Carl-Daniel Hailfinger
Hi,
I'm trying to find out which external programmers should be supported next.
1. There was talk of an AVR-based new programmer using the serprog
protocol on IRC by someone with the nick "coldelectrons", but I have no
idea if he/she is reading this mail. IMHO more hardware using the
serprog protocol is always a good idea.
2. All those Willem/Sivava variants. People regularly request those, but
I don't think anyone in here owns the hardware.
3. RayeR's SPIPGM. I have a preliminary patch which could work, but I
don't have the hardware. Will send the patch to the list soon.
4. LPC^2, Milksop, CheapLPC and other programmers from the Xbox modding
community.
5. Dozens of SPI programmer hardware projects scattered over the net.
Too many to count, and I'm not sure which of them has more than one user.
In general, it seems creating a new programmer hardware design is like
writing IRC clients: A nice way to get started in the field. I have no
problems merging flashrom support for all of them, but I won't implement
support for all of them myself.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
3 years, 2 months
[PATCH] Add git support to the Makefile
by Carl-Daniel Hailfinger
flashrom relies on svn to export tarballs and only prints the last svn
revision in the version message even if flashrom is in a git tree.
Print extended version information (version, svn revision, git hash,
repository URL).
Allow exporting from git trees.
This should make git users first-class citizens like svn users.
Side note: If anyone has an idea how to make the export target more
beautiful (80 column limit etc.), please tell me.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Index: flashrom-gitfriendly/Makefile
===================================================================
--- flashrom-gitfriendly/Makefile (Revision 1145)
+++ flashrom-gitfriendly/Makefile (Arbeitskopie)
@@ -97,13 +97,15 @@
# of the checked out flashrom files.
# Note to packagers: Any tree exported with "make export" or "make tarball"
# will not require subversion. The downloadable snapshots are already exported.
-SVNVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/\([0-9]*\).*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown)
+SCMVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/\([0-9]*\).*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown)
+SCMEXTVERSION := $(shell LC_ALL=C git rev-parse HEAD 2>/dev/null | sed 's/^./-\0/')
+SCMURL := $(shell LC_ALL=C svn info 2>/dev/null | grep URL: | sed 's/.*URL:[[:blank:]]*//' | grep ^. || LC_ALL=C git remote show origin 2>/dev/null |grep URL: | sed 's/.*URL:[[:blank:]]*//' | grep ^. || echo unknown )
RELEASE := 0.9.2
-VERSION := $(RELEASE)-r$(SVNVERSION)
+VERSION := $(RELEASE)-r$(SCMVERSION)$(SCMEXTVERSION)
RELEASENAME ?= $(VERSION)
-SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"'
+SCMDEF := -D'FLASHROM_VERSION="$(VERSION)"' -D'FLASHROM_SCMURL="$(SCMURL)"'
# Always enable internal/onboard support for now.
CONFIG_INTERNAL ?= yes
@@ -310,7 +312,7 @@
TAROPTIONS = $(shell LC_ALL=C tar --version|grep -q GNU && echo "--owner=root --group=root")
%.o: %.c .features
- $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -o $@ -c $<
+ $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SCMDEF) -o $@ -c $<
# Make sure to add all names of generated binaries here.
# This includes all frontends and libflashrom.
@@ -420,9 +422,12 @@
export:
@rm -rf $(EXPORTDIR)/flashrom-$(RELEASENAME)
- @svn export -r BASE . $(EXPORTDIR)/flashrom-$(RELEASENAME)
- @sed "s/^SVNVERSION.*/SVNVERSION := $(SVNVERSION)/" Makefile >$(EXPORTDIR)/flashrom-$(RELEASENAME)/Makefile
- @LC_ALL=C svn log >$(EXPORTDIR)/flashrom-$(RELEASENAME)/ChangeLog
+ @svn export -r BASE . $(EXPORTDIR)/flashrom-$(RELEASENAME) 2>/dev/null || git checkout-index -a -f --prefix=$(EXPORTDIR)/flashrom-$(RELEASENAME)/
+ @# If SCMVERSION or SCMEXTVERSION contain a slash or SCMURL contains a hash, this will explode
+ @sed "s/^SCMVERSION.*/SCMVERSION := $(SCMVERSION)/;s/^SCMEXTVERSION.*/SCMEXTVERSION := $(SCMEXTVERSION)/;s#^SCMURL.*#SCMURL := $(SCMURL)#" Makefile >$(EXPORTDIR)/flashrom-$(RELEASENAME)/Makefile
+ @# ChangeLog should be in English, but we want UTF-8 for names.
+ @( LC_ALL=en_US.UTF-8 svn log 2>/dev/null || LC_ALL=en_US.UTF-8 git log 2>/dev/null || echo "Unable to extract log from SCM" ) >$(EXPORTDIR)/flashrom-$(RELEASENAME)/ChangeLog
+ @rm -f $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitignore $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitattributes $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitmodules
@echo Exported $(EXPORTDIR)/flashrom-$(RELEASENAME)/
tarball: export
Index: flashrom-gitfriendly/flashrom.c
===================================================================
--- flashrom-gitfriendly/flashrom.c (Revision 1145)
+++ flashrom-gitfriendly/flashrom.c (Arbeitskopie)
@@ -1355,6 +1355,7 @@
void print_version(void)
{
msg_ginfo("flashrom v%s", flashrom_version);
+ msg_ginfo(" from " FLASHROM_SCMURL ",");
print_sysinfo();
}
@@ -1362,7 +1363,6 @@
{
msg_ginfo("flashrom is free software, get the source code at "
"http://www.flashrom.org\n");
- msg_ginfo("\n");
}
int selfcheck(void)
--
http://www.hailfinger.org/
5 years, 7 months
Re: [flashrom] [coreboot] Dualbios on GA-MA770-UD3
by Carl-Daniel Hailfinger
Hi Vadim,
thanks for your mail. I have added the flashrom mailing list in CC:
because we should develop a generic way to handle DualBIOS and similar
techniques.
On 09.04.2010 08:12, Vadim Girlin wrote:
> I'm going to try coreboot on Gigabyte GA-MA770-UD3.
> It's AMD 770 (RX780 / SB700).
>
> My motherboard supports hardware dual bios - with two chips on it.
> I'm going to try flashing backup chip and boot from it. It seems to be
> possible - I've tested it (flashing at least). Chips on this board could
> be switched by changing bit 0 at undocumented register EF on LDN 7 of
> IT8720. I can use slightly patched flashrom for accessing any chip I
> want without any problems. And this is tested many times.
>
> My idea is to use backup chip for debugging - that always keeps my
> chance to reboot from main bios chip. And removes the need for
> desoldering etc.
>
> And second problem is that original bios is checking second chip - and
> trying to recover it by flashing the bios from main chip on reboot?
> rewriting coreboot. AFAICS this could be solved by including some
> signatures etc. It seems to be easy to find out. May be someone is
> working on this?
>
> BTW I can send the patch for flashrom - but I think that with
> information I mentioned above somebody could make it much better than my
> ugly hack. I hope the regs should be the same for all latest Gigabyte
> MBs using IT8720/18
>
It would be great if you could send that patch. It will help us make a
flashrom design decision that works for all boards with multiple flash
chips.
By the way, some of us have good contacts at ITE, so we can ask ITE for
details about the undocumented registers.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
5 years, 7 months
2 flashes on SPI bus
by Andrei Dolnikov
Hello folks,
I would like to use a flashrom utility to access 2 serial flashes on
the SPI bus of my x86 board, but I'm struggling with the second one.
So I'm looking for any help, hints or advices which can help me to
solve this issue.
I have custom x86 board (Atom n450 CPU, ICH8M chipset) which have 2
serial flashes installed on it.
The first one is SST25VF016B and the second one is Numonyx M45PE16.
The M45PE16 is pretty the similar to the M25PE16.
Both this chips are connected to the SPI bus of the ICH8M chipset, the
CS (chip select) signal of the SST25VF is routed to the SPI_CS0 and
the CS signal of the M45PE16 is routed to the SPI_CS1.
I can successfully read, erase and write the SST flash.
Trying to figure out if flashrom utility can find the second Numonyx
flash I've added the proper description for it to the flashchips.c
(actually I've leaved it the same as for M25PE16 but changed model_id
field). Unfortunately it didn't help me at all.
So I'm wondering if flashrom can't find M45PE16 flash because of
cleared SPI_CS1 signal and how can I enable it?
Does flashrom utility support such kind of configurations or does it
simply searching for the flash on CS0?
Probably some of you have some ideas on enabling SPI_CS1 or even some
useful links etc.
Unfortunately the official Intel ICH8M documentation looks kind of
complicated and no so clear to me.
I'll of course digg into it but any help, hints or advices are highly
appreciated!
Thanks in advance,
xborodax.
6 years, 6 months
[PATCH 1/1] Simplify hwaccess.c
by Peter Lemenkov
This file is saturated with superfluous ifdefs arranged into
several nested levels. This in turn adds additional complexity
to process of adding another architecture.
I re-arranged all ifdef blocks and killed duplicated function
definitions. Also I added define(__amd64) to the list of x86-arches.
Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com>
---
hwaccess.c | 85 +++++++++++++++++++++--------------------------------------
1 files changed, 30 insertions(+), 55 deletions(-)
diff --git a/hwaccess.c b/hwaccess.c
index 3a61e60..4e87642 100644
--- a/hwaccess.c
+++ b/hwaccess.c
@@ -29,30 +29,47 @@
#endif
#include "flash.h"
+#if !( defined(__i386__) || \
+ defined(__x86_64__) || defined(__amd64) || \
+ defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) || \
+ defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__))
+#error Unknown architecture
+#endif
+
#if defined(__i386__) || defined(__x86_64__)
+#if defined(__FreeBSD__) || defined(__DragonFly__)
+int io_fd;
+#endif
+#endif
-/* sync primitive is not needed because x86 uses uncached accesses
- * which have a strongly ordered memory model.
- */
static inline void sync_primitive(void)
{
-}
-
-#if defined(__FreeBSD__) || defined(__DragonFly__)
-int io_fd;
+/* sync primitive is needed only on PowerPC because
+ * x86 uses uncached accesses which have a strongly ordered memory model
+ * /dev/mem on MIPS uses uncached accesses in mode 2 which has a strongly ordered memory model.
+ */
+#if defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+ /* Prevent reordering and/or merging of reads/writes to hardware.
+ * Such reordering and/or merging would break device accesses which
+ * depend on the exact access order.
+ */
+ asm("eieio" : : : "memory");
#endif
+}
void get_io_perms(void)
{
+/* PCI port I/O is not yet implemented on PowerPC or MIPS. */
+#if defined(__i386__) || defined(__x86_64__) || defined(__amd64)
#if defined(__DJGPP__)
/* We have full permissions by default. */
return;
#else
-#if defined (__sun) && (defined(__i386) || defined(__amd64))
+#if defined (__sun)
if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) {
#elif defined(__FreeBSD__) || defined (__DragonFly__)
if ((io_fd = open("/dev/io", O_RDWR)) < 0) {
-#else
+#else
if (iopl(3) != 0) {
#endif
msg_perr("ERROR: Could not get I/O privileges (%s).\n"
@@ -65,60 +82,18 @@ void get_io_perms(void)
exit(1);
}
#endif
+#endif
}
void release_io_perms(void)
{
+/* PCI port I/O is not yet implemented on PowerPC or MIPS. */
+#if defined(__i386__) || defined(__x86_64__) || defined(__amd64)
#if defined(__FreeBSD__) || defined(__DragonFly__)
close(io_fd);
#endif
-}
-
-#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
-
-static inline void sync_primitive(void)
-{
- /* Prevent reordering and/or merging of reads/writes to hardware.
- * Such reordering and/or merging would break device accesses which
- * depend on the exact access order.
- */
- asm("eieio" : : : "memory");
-}
-
-/* PCI port I/O is not yet implemented on PowerPC. */
-void get_io_perms(void)
-{
-}
-
-/* PCI port I/O is not yet implemented on PowerPC. */
-void release_io_perms(void)
-{
-}
-
-#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
-
-/* sync primitive is not needed because /dev/mem on MIPS uses uncached accesses
- * in mode 2 which has a strongly ordered memory model.
- */
-static inline void sync_primitive(void)
-{
-}
-
-/* PCI port I/O is not yet implemented on MIPS. */
-void get_io_perms(void)
-{
-}
-
-/* PCI port I/O is not yet implemented on MIPS. */
-void release_io_perms(void)
-{
-}
-
-#else
-
-#error Unknown architecture
-
#endif
+}
void mmio_writeb(uint8_t val, void *addr)
{
--
1.7.2.3
6 years, 6 months
[PATCH] Make satasii driver more robust
by David Borg
Sorry, forgot to CC.the list.
Updated patch to apply cleanly against latest revision (1151) and
changed the string as pointed out by Rudolf Marek.
Regards,
David
>-----BEGIN PGP SIGNED MESSAGE-----
>Hash: SHA1
>
>Hi thanks for doing that.
>
>Carl-Daniel Hailfinger wrote:
>> Make the satasii driver more robust.
>>
>> Untested.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2...(a)gmx.net>
>>
>> Index: flashrom-satasii_robust/satasii.c
>> ===================================================================
>> --- flashrom-satasii_robust/satasii.c (Revision 1005)
>> +++ flashrom-satasii_robust/satasii.c (Arbeitskopie)
>> @@ -44,6 +44,7 @@
>> {
>> uint32_t addr;
>> uint16_t reg_offset;
>> + uint32_t tmp;
>>
>> get_io_perms();
>>
>> @@ -59,12 +60,19 @@
>> reg_offset = 0x50;
>> }
>>
>> - sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;
>> + sii_bar = physmap("SATA SiI registers", addr, 0x100) + reg_offset;
>>
>> /* Check if ROM cycle are OK. */
>> if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26))))
>> msg_pinfo("Warning: Flash seems unconnected.\n");
>>
>> + msg_pdbg("Using BAR5 access method.\n");
>> + tmp = pci_read_long(pcidev_dev, 0x40) & (1 << 1);
>> + msg_pdbg("BAR5 Indirect Access is %snabled\n", tmp ? "en" : "dis");
>> + /* This bit has contradicting definitions in the 3512 datasheet. */
>
>this looks strange you get dissnabled or ensabled ;)
>
>> + tmp = pci_read_long(pcidev_dev, 0x88) & (1 << 16);
>> + msg_pdbg("BAR5 Access is %snabled\n", tmp ? "en" : "dis");
>
>This Reg is EN_66 in other controllers so I guess it just this and not the
>BA5_EN. It looks like it is driven by strap resistor only anyway.
>
>Interesting would be to test if BA5_EN is not enabled if you can access it
>through indirect access through C0/C4 regs.
>
>Thanks,
>Rudolf
>
>
>> +
>> buses_supported = CHIP_BUSTYPE_PARALLEL;
>>
>> return 0;
>> @@ -81,6 +89,7 @@
>> void satasii_chip_writeb(uint8_t val, chipaddr addr)
>> {
>> uint32_t ctrl_reg, data_reg;
>> + int i = 0;
>>
>> while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
>>
>> @@ -92,12 +101,19 @@
>> mmio_writel(data_reg, (sii_bar + 4));
>> mmio_writel(ctrl_reg, sii_bar);
>>
>> - while (mmio_readl(sii_bar) & (1 << 25)) ;
>> + while (mmio_readl(sii_bar) & (1 << 25)) {
>> + if (++i > 10000) {
>> + msg_perr("%s: control reg stuck at %08x, aborting\n",
>> + __func__, mmio_readl(sii_bar));
>> + break;
>> + }
>> + }
>> }
>>
>> uint8_t satasii_chip_readb(const chipaddr addr)
>> {
>> uint32_t ctrl_reg;
>> + int i = 0;
>>
>> while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
>>
>> @@ -107,7 +123,13 @@
>>
>> mmio_writel(ctrl_reg, sii_bar);
>>
>> - while (mmio_readl(sii_bar) & (1 << 25)) ;
>> + while (mmio_readl(sii_bar) & (1 << 25)) {
>> + if (++i > 10000) {
>> + msg_perr("%s: control reg stuck at %08x, aborting\n",
>> + __func__, mmio_readl(sii_bar));
>> + break;
>> + }
>> + }
>>
>> return (mmio_readl(sii_bar + 4)) & 0xff;
>> }
>>
>>
>-----BEGIN PGP SIGNATURE-----
>Version: GnuPG v1.4.10 (GNU/Linux)
>Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
>
>iEYEARECAAYFAkv4VwUACgkQ3J9wPJqZRNU4BQCfYmc1fp2kmy5SjQHjirrsKP82
>enkAoKQLbvmaCGs6/qNfawamobV7RayX
>=7NEj
>-----END PGP SIGNATURE-----
>
--
David Borg
6 years, 7 months
[PATCH] Add Winbond SuperI/O detection
by Carl-Daniel Hailfinger
Add Winbond Super I/O detection and hook it up to the generic Super I/O
detection framework.
Incomplete and untested, but at least it shouldn't break anything.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Index: flashrom-winbond_superio_detect/flash.h
===================================================================
--- flashrom-winbond_superio_detect/flash.h (Revision 1064)
+++ flashrom-winbond_superio_detect/flash.h (Arbeitskopie)
@@ -350,6 +350,7 @@
/* board_enable.c */
void w836xx_ext_enter(uint16_t port);
void w836xx_ext_leave(uint16_t port);
+struct superio probe_superio_winbond(void);
uint8_t sio_read(uint16_t port, uint8_t reg);
void sio_write(uint16_t port, uint8_t reg, uint8_t data);
void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
@@ -388,7 +389,8 @@
};
extern struct superio superio;
#define SUPERIO_VENDOR_NONE 0x0
-#define SUPERIO_VENDOR_ITE 0x1
+#define SUPERIO_VENDOR_WINBOND 0x1
+#define SUPERIO_VENDOR_ITE 0x2
struct pci_dev *pci_dev_find_filter(struct pci_filter filter);
struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class);
struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
Index: flashrom-winbond_superio_detect/internal.c
===================================================================
--- flashrom-winbond_superio_detect/internal.c (Revision 1064)
+++ flashrom-winbond_superio_detect/internal.c (Arbeitskopie)
@@ -104,12 +104,14 @@
void probe_superio(void)
{
- superio = probe_superio_ite();
+ superio = probe_superio_winbond();
#if 0
- /* Winbond Super I/O code is not yet available. */
+ /* ITE probe causes SMSC LPC47N217 to power off the serial UART. */
if (superio.vendor == SUPERIO_VENDOR_NONE)
- superio = probe_superio_winbond();
+ superio = probe_superio_smsc();
#endif
+ if (superio.vendor == SUPERIO_VENDOR_NONE)
+ superio = probe_superio_ite();
}
#endif
Index: flashrom-winbond_superio_detect/board_enable.c
===================================================================
--- flashrom-winbond_superio_detect/board_enable.c (Revision 1064)
+++ flashrom-winbond_superio_detect/board_enable.c (Arbeitskopie)
@@ -229,22 +229,59 @@
address, but takes no effort to make sure the chip is really a
Winbond Super I/O */
-static const struct winbond_chip * winbond_superio_detect(uint16_t base)
+uint8_t probe_id_winbond(uint16_t port)
{
uint8_t chipid;
+
+ w836xx_ext_enter(port);
+ chipid = sio_read(port, 0x20);
+ w836xx_ext_leave(port);
+
+ return chipid;
+}
+
+#define WINBOND_SUPERIO_PORT1 0x2e
+#define WINBOND_SUPERIO_PORT2 0x4e
+
+struct superio probe_superio_winbond(void)
+{
+ struct superio ret = {};
+ uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
+ uint16_t *i = winbond_ports;
+
+ ret.vendor = SUPERIO_VENDOR_WINBOND;
+ for (; *i; i++) {
+ ret.port = *i;
+ ret.model = probe_id_winbond(ret.port);
+ switch (ret.model) {
+ case WINBOND_W83627HF_ID:
+ case WINBOND_W83627EHF_ID:
+ case WINBOND_W83627THF_ID:
+ msg_pinfo("Found Winbond Super I/O, id %02hx\n",
+ ret.model);
+ return ret;
+ }
+ }
+
+ /* No good ID found. */
+ ret.vendor = SUPERIO_VENDOR_NONE;
+ ret.port = 0;
+ ret.model = 0;
+ return ret;
+}
+
+static const struct winbond_chip *winbond_superio_chipdef(void)
+{
const struct winbond_chip * chip = NULL;
int i;
- w836xx_ext_enter(base);
- chipid = sio_read(base, 0x20);
for (i = 0; i < ARRAY_SIZE(winbond_chips); i++)
- if (winbond_chips[i].device_id == chipid)
+ if (winbond_chips[i].device_id == superio.model)
{
chip = &winbond_chips[i];
break;
}
- w836xx_ext_leave(base);
return chip;
}
@@ -259,7 +296,7 @@
int port = pin / 10;
int bit = pin % 10;
- chip = winbond_superio_detect(base);
+ chip = winbond_superio_chipdef();
if (!chip) {
msg_perr("\nERROR: No supported Winbond Super I/O found\n");
return -1;
--
http://www.hailfinger.org/
6 years, 10 months
[PATCH] W83697xx superio flash enable
by David Borg
Adds a function to enable the flash interface on w83697xx superio's.
Still needs to be hooked up to the superio detection framework though.
Signed-off-by: David Borg <borg.db(a)gmail.com>
6 years, 10 months
Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Carl-Daniel Hailfinger
Hi Mike,
On 23.02.2010 05:45, Spangler, Mike T wrote:
> I can probe with a continuity tester, but would need to know specific
> pin locations to try. Do you have any generic info on doing this?
Yes (well, I'd have to write up something), but the solution mentioned
by Michael is way easier, so I'll wait until Michael has diagnosed the
GPIO settings from the flashrom run on factory BIOS.
Regards,
Carl-Daniel
--
"I do consider assignment statements and pointer variables to be among
computer science's most valuable treasures."
-- Donald E. Knuth
7 years, 1 month
AMD SB7xx/SB8xx w/IMC: enable specs
by Joshua Roys
Hello all,
The specific board this is for is the Supermicro H8DGT. Attached is
only the specification, which is not guaranteed to be correct. Use with
care.
Also, after using this, you may want to turn off and unplug the computer
for a few minutes to restore the correct operational state.
The AMD SB700/710/750 Register Reference Guide (#43009) was used as a
reference.
Thanks,
Josh
7 years, 2 months
