we're hitting the 80 column limit in our code in ways which actually
reduce readability for the code. Examples are various multiline messages
and complicated nested code where refactoring to a separate function
doesn't make sense.
Keeping the old 80 column limit is not really an option anymore.
Standard terminal sizes have one of 80, 100 or 132 columns.
Given the monitor resolutions many people have nowadays, I think it is
safe to say that you can fit two xterms with 100 columns horizonally
next to each other. 100 columns should also be sufficient for a msg_p*
of roughly 80 columns of text.
132 columns provide more leeway, but IMHO that would be too wide for
good readability (and my screen can't fit two xterms side-by-side anymore).
Of course some files have sections where any column limit is not
acceptable (board lists etc.), but the column limit violations should be
limited to the affected file sections, not whole files.
I'd like to get this decided today or tomorrow so we know where we need
line breaks in Stefan Tauner's new struct flashchip patch.
I have a spansion S25FL128P......X chip and can do some tests.
The "problem" is that i don't know if its an 0 or an 1.
On the chip i see only "FL128PIF" and one line lower i see "00299012 C".
Probing works (id1 0x01, id2 0x2018):
Calibrating delay loop... OK.
serprog: Programmer name is "serprog-duino"
Found Spansion flash chip "S25FL128P......0" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL128P......1" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL128S......0" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL128S......1" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL129P......0" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL129P......1" (16384 kB, SPI) on serprog.
Multiple flash chip definitions match the detected chip(s):
"S25FL128P......0", "S25FL128P......1", "S25FL128S......0",
"S25FL128S......1", "S25FL129P......0", "S25FL129P......1"
Please specify which chip definition to use with the -c <chipname> option.
BTW: Chip was fund on a Dell-Systemboard.
FOSDEM 2017 deadlines are soon.
Do we want to have a full developer room, a talk or just a stand?
Unfortunately I won't be able to attend, so someone else will have to be
the formal contact for organizing our stand/devroom/talk. I will help
with submitting proposals if this is desired by the person organizing
Who is willing to take care of our FOSDEM 2017 presence?
Developer Rooms: 9 September
Main Track Talks: 10 October
Stands: 31 October
Lightning talks: 25 November
This is actually the management engine at play and is a known issue.
You'll have to ask Intel about this logic to judge whether it's a feature
or a bug...
On Wed, Aug 31, 2016 at 7:49 AM, Brishchik Gupta <brishchik(a)mail.com> wrote:
> Device: Acer C720-3605 Chromebook (Haswell) with Winbond W25Q64 8MB
> firmware flash
> Description of issue --- The following behavior is observed:
> 1. If write protect is disabled (either in hardware i.e. screw removed, or
> in software i.e. status.srp0 == 0 == status.srp1, or in both hardware and
> software) AND there is a non-null write protect range (set by status
> register bits BP0/BP1/BP2/TB/SEC), then upon power cycled reboot, the
> status registers get completely cleared (to 0x0000).
> 2. If write protect is disabled in hardware but not in software and the
> write protect range is null (so status registers == 0x0080), then a power
> cycled reboot preserves the status registers (i.e. the value is still
> 0x0080 after reboot).
> Is the above behavior a feature or a bug?
> I can post logs (e.g. outputs of "flashrom --wp-status") if necessary.
> Best regards,
> Brishchik Gupta
> flashrom mailing list
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
Device: Acer C720-3605 Chromebook (Haswell) with Winbond W25Q64 8MB firmware flash
Description of issue --- The following behavior is observed:
1. If write protect is disabled (either in hardware i.e. screw removed,
or in software i.e. status.srp0 == 0 == status.srp1, or in both hardware
and software) AND there is a non-null write protect range (set by
status register bits BP0/BP1/BP2/TB/SEC), then upon power cycled reboot,
the status registers get completely cleared (to 0x0000).
2. If write protect is disabled in hardware but not in software
and the write protect range is null (so status registers == 0x0080),
then a power cycled reboot preserves the status registers
(i.e. the value is still 0x0080 after reboot).
Is the above behavior a feature or a bug?
I can post logs (e.g. outputs of "flashrom --wp-status") if necessary.
flashrom v0.9.6.1-r1563 on Linux 3.19.0-32-generic (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org
flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian
Command line (3 args): flashrom --programmer internal -V
Calibrating delay loop... OS timer resolution is 1 usecs, 1273M loops per
second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus
= 10003 us, 4 myus = 10 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "LENOVO"
DMI string system-product-name: "80LK"
DMI string system-version: "Lenovo B51-30"
DMI string baseboard-manufacturer: "LENOVO"
DMI string baseboard-product-name: "Lenovo B51-30"
DMI string baseboard-version: "SDK0J40679 WIN"
DMI string chassis-type: "Notebook"
Laptop detected via DMI.
W836xx enter config mode worked or we were already in config mode. W836xx
leave config mode had no effect.
Active config mode, unknown reg 0x20 ID: fc.
Please send the output of "flashrom -V" to
flashrom(a)flashrom.org with W836xx: your board name: flashrom -V
as the subject to help us finish support for your Super I/O. Thanks.
I try to reprogram BIOS of ThinkPad X200 notebook "in situ" by
OrangePi PC (its SPI bus).
I cannot read it consistently even if on low frequency 32 kHz.
I use 100 mm short wires.
On the help page:
there is recommendation about matching the impedance of inputs & wires:
"The impedances of the wires/traces do not match the impedances of the
input pins (of either the circuit/chip on the mainboard or the
external programmer). Try using shorter wires, adding small (<100 Ohm)
series resistors or parallel capacitors (<20pF) as near as possible to
the input pins (this includes also the MISO line which ends near the
programmer) and/or ask someone who has experience with high frequency
I know basic of electrical engineering & a bit about electronic, but I
am very very far from expert.
I try to search this mailing list archives for words "capacitor" or
"capacitors", but with no demanded answer.
I try google it, e. g. :
system")(capacitor|impedance)"input" -crystal -oscillator
but it found me only articles about
which I think that I quite understand, yet
or documentation from Actel, Advanced Micro Devices, Altera, Atmel,
CheckSum, CML Microcircuits, Cypress Semiconductor, Elnec, LAPIS
Semiconductor, Lattice Semiconductor, Microchip Technology, Microsemi,
Numonyx, Silicon Labs, STMicroelectronics, Texas Instruments, Xilinx
etc. sometimes about In-System Programming, but never about these
What is better, resistor or capacitor (or combination)?
How to connect them? (Resistor is clear - in series with the wire. But
what about capacitor? Parallel with which?)
On page (bottom "Notes about stability")
there is recommendation about foiled twisted pair with link to image
- should not be second wire of the pair respectively foil connected to
957 01 Bánovce nad Bebravou 1
(cellular: +421 940 872 846, short messages only)
I have little problem And I would like to ask for help if is possible.
I need flash 2 types of eeprom, and I bought cheap Ch341A programmer as I
see that he "supports" EON 25F16 and EON 25F80 but I have Issue I try with
windows and with flashrom but I canno't get detection of ic's. I check
Connection of every pin between eeprom flash and ch341A and it is GOOD. in
windows I use software that I get with it but only that I get working is
detection of ch341a nothing more. Always i get eepron not found or
manufactures id FF or memory id FF hope you get point.
So I read in datasheet that eon ic's have protection blocks for write read
like 512 bit sometnig. Is it there any way to shoot that command for
enabling write read or is it programmer(CH341A) Fault .