I'm trying to find out which external programmers should be supported next.
1. There was talk of an AVR-based new programmer using the serprog
protocol on IRC by someone with the nick "coldelectrons", but I have no
idea if he/she is reading this mail. IMHO more hardware using the
serprog protocol is always a good idea.
2. All those Willem/Sivava variants. People regularly request those, but
I don't think anyone in here owns the hardware.
3. RayeR's SPIPGM. I have a preliminary patch which could work, but I
don't have the hardware. Will send the patch to the list soon.
4. LPC^2, Milksop, CheapLPC and other programmers from the Xbox modding
5. Dozens of SPI programmer hardware projects scattered over the net.
Too many to count, and I'm not sure which of them has more than one user.
In general, it seems creating a new programmer hardware design is like
writing IRC clients: A nice way to get started in the field. I have no
problems merging flashrom support for all of them, but I won't implement
support for all of them myself.
thanks for your mail. I have added the flashrom mailing list in CC:
because we should develop a generic way to handle DualBIOS and similar
On 09.04.2010 08:12, Vadim Girlin wrote:
> I'm going to try coreboot on Gigabyte GA-MA770-UD3.
> It's AMD 770 (RX780 / SB700).
> My motherboard supports hardware dual bios - with two chips on it.
> I'm going to try flashing backup chip and boot from it. It seems to be
> possible - I've tested it (flashing at least). Chips on this board could
> be switched by changing bit 0 at undocumented register EF on LDN 7 of
> IT8720. I can use slightly patched flashrom for accessing any chip I
> want without any problems. And this is tested many times.
> My idea is to use backup chip for debugging - that always keeps my
> chance to reboot from main bios chip. And removes the need for
> desoldering etc.
> And second problem is that original bios is checking second chip - and
> trying to recover it by flashing the bios from main chip on reboot?
> rewriting coreboot. AFAICS this could be solved by including some
> signatures etc. It seems to be easy to find out. May be someone is
> working on this?
> BTW I can send the patch for flashrom - but I think that with
> information I mentioned above somebody could make it much better than my
> ugly hack. I hope the regs should be the same for all latest Gigabyte
> MBs using IT8720/18
It would be great if you could send that patch. It will help us make a
flashrom design decision that works for all boards with multiple flash
By the way, some of us have good contacts at ITE, so we can ask ITE for
details about the undocumented registers.
On Mon, 30 May 2011 02:45:44 +0200
Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote:
> this patch also changes the display width of all addresses in physmap.c to 16 hex characters.
> FIXME: what about unmappings?
> munmap is safe.
> djgpp's __dpmi_free_physical_address_mapping: unknown.
> DirectHW's unmap_physical: unknown.
> FIXME: jakllsch suggested using PRIx64 instead of x, because it's more portable
FIXME: in the case we can not map and 'mayfail' is true we should return
ERROR_PTR instead of ERROR_PTR + diff
Kind regards/Mit freundlichen Grüßen, Stefan Tauner
I would like to use a flashrom utility to access 2 serial flashes on
the SPI bus of my x86 board, but I'm struggling with the second one.
So I'm looking for any help, hints or advices which can help me to
solve this issue.
I have custom x86 board (Atom n450 CPU, ICH8M chipset) which have 2
serial flashes installed on it.
The first one is SST25VF016B and the second one is Numonyx M45PE16.
The M45PE16 is pretty the similar to the M25PE16.
Both this chips are connected to the SPI bus of the ICH8M chipset, the
CS (chip select) signal of the SST25VF is routed to the SPI_CS0 and
the CS signal of the M45PE16 is routed to the SPI_CS1.
I can successfully read, erase and write the SST flash.
Trying to figure out if flashrom utility can find the second Numonyx
flash I've added the proper description for it to the flashchips.c
(actually I've leaved it the same as for M25PE16 but changed model_id
field). Unfortunately it didn't help me at all.
So I'm wondering if flashrom can't find M45PE16 flash because of
cleared SPI_CS1 signal and how can I enable it?
Does flashrom utility support such kind of configurations or does it
simply searching for the flash on CS0?
Probably some of you have some ideas on enabling SPI_CS1 or even some
useful links etc.
Unfortunately the official Intel ICH8M documentation looks kind of
complicated and no so clear to me.
I'll of course digg into it but any help, hints or advices are highly
Thanks in advance,
#5: Winbond W25Q128 for ICH
Reporter: rheneus.paul@… | Owner: hailfinger
Type: defect | Status: new
Priority: critical | Milestone:
Component: flashrom | Version:
Keywords: | Dependencies:
Patch Status: there is no patch |
I could not use flashrom 0.9.3 -r1205 to detect Winbond W25Q128 to program
BIOS. Attached the read log
Just by adding WINBOND_NEX_W25Q128 0x4018 in flashchips.c for W25Q128,
similar to W25Q64 throws run Opcode 0x3 error for read.
Attached Verbose log of read
Ticket URL: <http://www.flashrom.org/trac/flashrom/ticket/5>
I have an ASUS P5LD2-VM, and I try to update bios, first with flashrom
v0.9.2-r1028 ( http://paste.flashrom.org/view.php?id=489 )
then with 0.9.3 ( http://paste.flashrom.org/view.php?id=490 also, the
ROM is at http://paste.flashrom.org/uploads/491.bin )
Writing flash chip... Erasing flash chip... Looking at blockwise erase
function 0... trying... 0x000000-0x000fff, 0x001000-0x001fff,
0x002000-0x002fff, 0x003000-0xff, 0x004000-0x004fff, 0x005000-0x005fff,
ERASE FAILED at 0x00005760! Expected=0xff, Read=0x50, failed byte count
from 0x00005000-0x00005fff: 0x87a
Can you help whit this?
I'm carco on freenode/#flashrom channel