This is code from a an old board enable that i sent in 3 weeks ago. This
board enable was not necessary (as flashing worked just fine without it
too). But this function was also used to clean up the board enable for
the epox ep bx3.
I have tracked down the person for whom i wrote this board enable 2
years ago: irc user nyu, aka Robert Millan.
Robert, can you verify that this code is not a regression for you?
Uwe, in the original mail thread
(http://www.coreboot.org/pipermail/coreboot/2009-June/049789.html) you
had several suggestions. I have taken over unsigned int and the
bitshift, but i do mot like to put "PIIX4{,E,M}" everywhere.
"PIIX4{,E,M}" all over clutters up the place, and i fear that printing
this to the user will generate more confusion than it will ever remove.
Instead i have adjusted the initial function comment to mention this so
that developers can rest assured in future that this will also be valid
for their future board enables.
Luc Verhaegen.
Resending this patch to the newly formed flashrom ml. Ron already
kindly acked this patch.
Mateusz, the owner of this board gave me a brief comment on irc stating
that it didn't work. Which is also the last i heard from him.
Mateusz, get back to us and get us at least the flashrom output.
Luc Verhaegen.
If a chip is not on the RDID generic vendor list nor on the REMS
specific ID list, flashrom will claim that no chip is there. Handle
these cases gracefully. flashrom will ignore generic matches if a
specific chip was found, so this will have no impact on supported chips,
but help a lot for a first quick analysis by the user or developer. The
only drawback is that unknown chips may be recognized multiple times
until they are added to flashchips.[ch].
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Index: flashrom-spi_totally_generic_probe/flashchips.c
===================================================================
--- flashrom-spi_totally_generic_probe/flashchips.c (Revision 664)
+++ flashrom-spi_totally_generic_probe/flashchips.c (Arbeitskopie)
@@ -3167,5 +3167,32 @@
.read = NULL,
},
+ {
+ .vendor = "Generic",
+ .name = "unknown SPI chip (RDID)",
+ .bustype = CHIP_BUSTYPE_SPI,
+ .manufacture_id = GENERIC_MANUF_ID,
+ .model_id = GENERIC_DEVICE_ID,
+ .total_size = 0,
+ .page_size = 256,
+ .tested = TEST_BAD_PREW,
+ .probe = probe_spi_rdid,
+ .erase = NULL,
+ .write = NULL,
+ },
+ {
+ .vendor = "Generic",
+ .name = "unknown SPI chip (REMS)",
+ .bustype = CHIP_BUSTYPE_SPI,
+ .manufacture_id = GENERIC_MANUF_ID,
+ .model_id = GENERIC_DEVICE_ID,
+ .total_size = 0,
+ .page_size = 256,
+ .tested = TEST_BAD_PREW,
+ .probe = probe_spi_rems,
+ .erase = NULL,
+ .write = NULL,
+ },
+
{ NULL }
};
Index: flashrom-spi_totally_generic_probe/flashchips.h
===================================================================
--- flashrom-spi_totally_generic_probe/flashchips.h (Revision 664)
+++ flashrom-spi_totally_generic_probe/flashchips.h (Arbeitskopie)
@@ -34,6 +34,7 @@
* SPI parts have 16-bit device IDs if they support RDID.
*/
+#define GENERIC_MANUF_ID 0xffff /* Check if there is a vendor ID */
#define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */
#define ALLIANCE_ID 0x52 /* Alliance Semiconductor */
Index: flashrom-spi_totally_generic_probe/spi.c
===================================================================
--- flashrom-spi_totally_generic_probe/spi.c (Revision 664)
+++ flashrom-spi_totally_generic_probe/spi.c (Arbeitskopie)
@@ -274,6 +274,11 @@
GENERIC_DEVICE_ID == flash->model_id)
return 1;
+ /* Test if there is any vendor ID. */
+ if (GENERIC_MANUF_ID == flash->manufacture_id &&
+ id1 != 0xff)
+ return 1;
+
return 0;
}
@@ -329,6 +334,11 @@
GENERIC_DEVICE_ID == flash->model_id)
return 1;
+ /* Test if there is any vendor ID. */
+ if (GENERIC_MANUF_ID == flash->manufacture_id &&
+ id1 != 0xff)
+ return 1;
+
return 0;
}
--
http://www.hailfinger.org/
See patch.
Please do NOT try write/erase on any important cards yet, it doesn't
seem to fully work properly yet and you could "brick" your card.
I tested a "RIVA TNT2 Model 64/Model 64 Pro", which successfully
identified and read a Winbond W29C011 chip, but erase and write behaved
incorrect and I finally bricked the card.
Will look into recovery soon (likely will work via software I assume,
no hardware hacking strictly required I think/hope, we'll see).
As for the list of supported cards: I have no idea which of those may
work (i.e. have the same flash programming interface), maybe none, maybe
all of them (and lots more NVIDIA cards), we'll see as soon as others
test more cards.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.dehttp://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Hello,
I have tried to flash the BIOS of my motherboard. It's a Gigabyte
G33M-DS2R (ICH9R + SST SST25VF080B" (1024 KB)).
[root@scarabee benjamin]# flashrom --version
flashrom v0.9.0
(on Fedora 11 x86_64)
Here is the log of the flash (my motherboard was previously in version F7) :
flashrom --write ./G33MDS2R.F8
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel ICH9R", enabling flash write... OK.
Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000.
===
This flash part has status UNTESTED for operations: READ ERASE WRITE
Please email a report to flashrom(a)coreboot.org if any of the above
operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Flash image seems to be a legacy BIOS. Disabling checks.
Programming page:
[root@scarabee motherboard_bios_ga-g33m-ds2r_f8]#
and I check the BIOS :
[root@scarabee motherboard_bios_ga-g33m-ds2r_f8]# flashrom --verify
./G33MDS2R.F8
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel ICH9R", enabling flash write... OK.
Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000.
===
This flash part has status UNTESTED for operations: READ ERASE WRITE
Please email a report to flashrom(a)coreboot.org if any of the above
operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... FAILED at 0x00000000! Expected=0x00, Read=0x01
[root@scarabee motherboard_bios_ga-g33m-ds2r_f8]#
and when I try to erase it :
[root@scarabee benjamin]# flashrom --erase
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel ICH9R", enabling flash write... OK.
Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000.
===
This flash part has status UNTESTED for operations: READ ERASE WRITE
Please email a report to flashrom(a)coreboot.org if any of the above
operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Erasing flash chip... FAILED!
ERROR at 0x00000000: Expected=0xff, Read=0x01
[root@scarabee benjamin]#
I can post the entire log (--write --verbose) if you want.
What can I do, is my BIOS really write or not ? Can I reboot ?
Thanks for your time.
Benjamin (from France)
Author: stepan
Date: 2009-07-30 15:32:26 +0200 (Thu, 30 Jul 2009)
New Revision: 669
Modified:
trunk/README
trunk/flashrom.8
trunk/flashrom.c
trunk/pcidev.c
Log:
The project's new home is flashrom.org now. Change all occurences in the
source code and documentation accordingly.
Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de>
Acked-by: Stefan Reinauer <stepan(a)coresystems.de>
Modified: trunk/README
===================================================================
--- trunk/README 2009-07-30 13:30:17 UTC (rev 668)
+++ trunk/README 2009-07-30 13:32:26 UTC (rev 669)
@@ -122,5 +122,5 @@
The official flashrom website is:
- http://coreboot.org/Flashrom
+ http://www.flashrom.org/
Modified: trunk/flashrom.8
===================================================================
--- trunk/flashrom.8 2009-07-30 13:30:17 UTC (rev 668)
+++ trunk/flashrom.8 2009-07-30 13:32:26 UTC (rev 669)
@@ -133,7 +133,7 @@
Same as
.BR \-\-list\-supported ,
but outputs the supported hardware in MediaWiki syntax, so that it can be
-easily pasted into the wiki page at http://coreboot.org/Flashrom.
+easily pasted into the wiki page at http://www.flashrom.org/.
.TP
.B "\-p, \-\-programmer <name>"
Specify the programmer device. Currently supported are:
@@ -217,9 +217,9 @@
(/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails.
.SH BUGS
Please report any bugs at
-.BR http://tracker.coreboot.org/trac/coreboot/newticket ","
-or on the coreboot mailing list
-.RB "(" http://coreboot.org/Mailinglist ")."
+.BR http://www.flashrom.org/trac/flashrom/newticket ","
+or on the flashrom mailing list
+.RB "(" http://www.flashrom.org/mailman/listinfo/flashrom ")."
.SH LICENCE
.B flashrom
is covered by the GNU General Public License (GPL), version 2. Some files are
Modified: trunk/flashrom.c
===================================================================
--- trunk/flashrom.c 2009-07-30 13:30:17 UTC (rev 668)
+++ trunk/flashrom.c 2009-07-30 13:32:26 UTC (rev 669)
@@ -780,7 +780,7 @@
printf(" WRITE");
printf("\n");
}
- printf("Please email a report to flashrom(a)coreboot.org if any "
+ printf("Please email a report to flashrom(a)flashrom.org if any "
"of the above operations\nwork correctly for you with "
"this flash part. Please include the flashrom\noutput "
"with the additional -V option for all operations you "
Modified: trunk/pcidev.c
===================================================================
--- trunk/pcidev.c 2009-07-30 13:30:17 UTC (rev 668)
+++ trunk/pcidev.c 2009-07-30 13:32:26 UTC (rev 669)
@@ -51,7 +51,7 @@
if (devs[i].status == PCI_NT) {
printf("===\nThis PCI device is UNTESTED. Please "
"report the 'flashrom -p xxxx' output \n"
- "to flashrom(a)coreboot.org if it works "
+ "to flashrom(a)flashrom.org if it works "
"for you. Thank you for your help!\n===\n");
}