July 2009 - flashrom - mail.coreboot.org

by Luc Verhaegen

This is code from a an old board enable that i sent in 3 weeks ago. This board enable was not necessary (as flashing worked just fine without it too). But this function was also used to clean up the board enable for the epox ep bx3. I have tracked down the person for whom i wrote this board enable 2 years ago: irc user nyu, aka Robert Millan. Robert, can you verify that this code is not a regression for you? Uwe, in the original mail thread (http://www.coreboot.org/pipermail/coreboot/2009-June/049789.html) you had several suggestions. I have taken over unsigned int and the bitshift, but i do mot like to put "PIIX4{,E,M}" everywhere. "PIIX4{,E,M}" all over clutters up the place, and i fear that printing this to the user will generate more confusion than it will ever remove. Instead i have adjusted the initial function comment to mention this so that developers can rest assured in future that this will also be valid for their future board enables. Luc Verhaegen.

10 years, 3 months

3
9
0 0

[Patch] Shuttle AK31

by Luc Verhaegen

Resending this patch to the newly formed flashrom ml. Ron already kindly acked this patch. Mateusz, the owner of this board gave me a brief comment on irc stating that it didn't work. Which is also the last i heard from him. Mateusz, get back to us and get us at least the flashrom output. Luc Verhaegen.

10 years, 3 months

3
6
0 0

[PATCH] Totally generic SPI chip match

by Carl-Daniel Hailfinger

If a chip is not on the RDID generic vendor list nor on the REMS specific ID list, flashrom will claim that no chip is there. Handle these cases gracefully. flashrom will ignore generic matches if a specific chip was found, so this will have no impact on supported chips, but help a lot for a first quick analysis by the user or developer. The only drawback is that unknown chips may be recognized multiple times until they are added to flashchips.[ch]. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_totally_generic_probe/flashchips.c =================================================================== --- flashrom-spi_totally_generic_probe/flashchips.c (Revision 664) +++ flashrom-spi_totally_generic_probe/flashchips.c (Arbeitskopie) @@ -3167,5 +3167,32 @@ .read = NULL, }, + { + .vendor = "Generic", + .name = "unknown SPI chip (RDID)", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = GENERIC_DEVICE_ID, + .total_size = 0, + .page_size = 256, + .tested = TEST_BAD_PREW, + .probe = probe_spi_rdid, + .erase = NULL, + .write = NULL, + }, + { + .vendor = "Generic", + .name = "unknown SPI chip (REMS)", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = GENERIC_DEVICE_ID, + .total_size = 0, + .page_size = 256, + .tested = TEST_BAD_PREW, + .probe = probe_spi_rems, + .erase = NULL, + .write = NULL, + }, + { NULL } }; Index: flashrom-spi_totally_generic_probe/flashchips.h =================================================================== --- flashrom-spi_totally_generic_probe/flashchips.h (Revision 664) +++ flashrom-spi_totally_generic_probe/flashchips.h (Arbeitskopie) @@ -34,6 +34,7 @@ * SPI parts have 16-bit device IDs if they support RDID. */ +#define GENERIC_MANUF_ID 0xffff /* Check if there is a vendor ID */ #define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */ #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ Index: flashrom-spi_totally_generic_probe/spi.c =================================================================== --- flashrom-spi_totally_generic_probe/spi.c (Revision 664) +++ flashrom-spi_totally_generic_probe/spi.c (Arbeitskopie) @@ -274,6 +274,11 @@ GENERIC_DEVICE_ID == flash->model_id) return 1; + /* Test if there is any vendor ID. */ + if (GENERIC_MANUF_ID == flash->manufacture_id && + id1 != 0xff) + return 1; + return 0; } @@ -329,6 +334,11 @@ GENERIC_DEVICE_ID == flash->model_id) return 1; + /* Test if there is any vendor ID. */ + if (GENERIC_MANUF_ID == flash->manufacture_id && + id1 != 0xff) + return 1; + return 0; } -- http://www.hailfinger.org/

10 years, 4 months

2
4
0 0

[PATCH] Add -p gfxnvidia for flashing NVIDIA graphics cards

by Uwe Hermann

See patch. Please do NOT try write/erase on any important cards yet, it doesn't seem to fully work properly yet and you could "brick" your card. I tested a "RIVA TNT2 Model 64/Model 64 Pro", which successfully identified and read a Winbond W29C011 chip, but erase and write behaved incorrect and I finally bricked the card. Will look into recovery soon (likely will work via software I assume, no hardware hacking strictly required I think/hope, we'll see). As for the list of supported cards: I have no idea which of those may work (i.e. have the same flash programming interface), maybe none, maybe all of them (and lots more NVIDIA cards), we'll see as soon as others test more cards. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

10 years, 6 months

3
3
0 0

[PATCH] Blockwise erase infrastructure

by Carl-Daniel Hailfinger

Blockwise erase infrastructure, 6th try. The description is pretty long and has not changed since last time. I can repost it if desired. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-eraseblocks/flash.h =================================================================== --- flashrom-eraseblocks/flash.h (Revision 664) +++ flashrom-eraseblocks/flash.h (Arbeitskopie) @@ -140,6 +140,17 @@ CHIP_BUSTYPE_UNKNOWN = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI, }; +/* + * How many different contiguous runs of erase blocks with one size each do + * we have for a given erase function? + */ +#define NUM_ERASEREGIONS 5 + +/* + * How many different erase functions do we have per chip? + */ +#define NUM_ERASEFUNCTIONS 5 + struct flashchip { const char *vendor; const char *name; @@ -168,6 +179,19 @@ /* Delay after "enter/exit ID mode" commands in microseconds. */ int probe_timing; int (*erase) (struct flashchip *flash); + + /* + * Erase blocks and associated erase function. The default entry is a + * chip-sized virtual block together with the chip erase function. + */ + struct block_eraser { + struct eraseblock{ + unsigned int size; /* Eraseblock size */ + unsigned int count; /* Number of contiguous blocks with that size */ + } eraseblocks[NUM_ERASEREGIONS]; + int (*block_erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); + } block_erasers[NUM_ERASEFUNCTIONS]; + int (*write) (struct flashchip *flash, uint8_t *buf); int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); @@ -383,6 +407,7 @@ #define printf_debug(x...) { if (verbose) printf(x); } void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); +int erase_flash(struct flashchip *flash); int min(int a, int b); int max(int a, int b); int check_erased_range(struct flashchip *flash, int start, int len); Index: flashrom-eraseblocks/flashchips.c =================================================================== --- flashrom-eraseblocks/flashchips.c (Revision 664) +++ flashrom-eraseblocks/flashchips.c (Arbeitskopie) @@ -1220,7 +1220,30 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = spi_block_erase_20, + }, + { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_52, + }, + { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_d8, + }, + { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, + { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -1236,7 +1259,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, + { + .eraseblocks = { {64 * 1024, 2} }, + .block_erase = spi_block_erase_d8, + }, + { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, + { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, Index: flashrom-eraseblocks/spi.c =================================================================== --- flashrom-eraseblocks/spi.c (Revision 664) +++ flashrom-eraseblocks/spi.c (Arbeitskopie) @@ -1006,7 +1006,7 @@ default: break; } - if (flash->erase(flash)) { + if (erase_flash(flash)) { fprintf(stderr, "ERASE FAILED!\n"); return -1; } Index: flashrom-eraseblocks/wbsio_spi.c =================================================================== --- flashrom-eraseblocks/wbsio_spi.c (Revision 664) +++ flashrom-eraseblocks/wbsio_spi.c (Arbeitskopie) @@ -197,7 +197,7 @@ return 1; } - if (flash->erase(flash)) { + if (erase_flash(flash)) { fprintf(stderr, "ERASE FAILED!\n"); return -1; } Index: flashrom-eraseblocks/w39v040c.c =================================================================== --- flashrom-eraseblocks/w39v040c.c (Revision 664) +++ flashrom-eraseblocks/w39v040c.c (Arbeitskopie) @@ -78,7 +78,7 @@ int page_size = flash->page_size; chipaddr bios = flash->virtual_memory; - if (flash->erase(flash)) { + if (erase_flash(flash)) { fprintf(stderr, "ERASE FAILED!\n"); return -1; } Index: flashrom-eraseblocks/sb600spi.c =================================================================== --- flashrom-eraseblocks/sb600spi.c (Revision 664) +++ flashrom-eraseblocks/sb600spi.c (Arbeitskopie) @@ -54,7 +54,7 @@ /* Erase first */ printf("Erasing flash before programming... "); - if (flash->erase(flash)) { + if (erase_flash(flash)) { fprintf(stderr, "ERASE FAILED!\n"); return -1; } Index: flashrom-eraseblocks/flashrom.c =================================================================== --- flashrom-eraseblocks/flashrom.c (Revision 664) +++ flashrom-eraseblocks/flashrom.c (Arbeitskopie) @@ -443,36 +443,66 @@ int erase_flash(struct flashchip *flash) { - uint32_t erasedbytes; - unsigned long size = flash->total_size * 1024; - unsigned char *buf = calloc(size, sizeof(char)); + int i, j, k, ret = 0, found = 0; + printf("Erasing flash chip... "); - if (NULL == flash->erase) { - printf("FAILED!\n"); + for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { + unsigned long done = 0; + struct block_eraser eraser = flash->block_erasers[k]; + + printf_debug("Looking at blockwise erase function %i... ", k); + if (!eraser.block_erase && !eraser.eraseblocks[0].count) { + printf_debug("not defined. " + "Looking for another erase function.\n"); + continue; + } + if (!eraser.block_erase && eraser.eraseblocks[0].count) { + printf_debug("eraseblock layout is known, but no " + "matching block erase function found. " + "Looking for another erase function.\n"); + continue; + } + if (eraser.block_erase && !eraser.eraseblocks[0].count) { + printf_debug("block erase function found, but " + "eraseblock layout is unknown. " + "Looking for another erase function.\n"); + continue; + } + found = 1; + printf_debug("trying... "); + for (i = 0; i < NUM_ERASEREGIONS; i++) { + /* count==0 for all automatically initialized array + * members so the loop below won't be executed for them. + */ + for (j = 0; j < eraser.eraseblocks[i].count; j++) { + ret = eraser.block_erase(flash, done + eraser.eraseblocks[i].size * j, eraser.eraseblocks[i].size); + if (ret) + break; + } + if (ret) + break; + } + /* If everything is OK, don't try another erase function. */ + if (!ret) + break; + } + /* If no block erase function was found or block erase failed, retry. */ + if ((!found || ret) && (flash->erase)) { + found = 1; + printf_debug("Trying whole-chip erase function... "); + ret = flash->erase(flash); + } + if (!found) { fprintf(stderr, "ERROR: flashrom has no erase function for this flash chip.\n"); return 1; } - flash->erase(flash); - /* FIXME: The lines below are superfluous. We should check the result - * of flash->erase(flash) instead. - */ - if (!flash->read) { - printf("FAILED!\n"); - fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n"); - return 1; - } else - flash->read(flash, buf, 0, size); - - for (erasedbytes = 0; erasedbytes < size; erasedbytes++) - if (0xff != buf[erasedbytes]) { - printf("FAILED!\n"); - fprintf(stderr, "ERROR at 0x%08x: Expected=0xff, Read=0x%02x\n", - erasedbytes, buf[erasedbytes]); - return 1; - } - printf("SUCCESS.\n"); - return 0; + if (ret) { + fprintf(stderr, "FAILED!\n"); + } else { + printf("SUCCESS.\n"); + } + return ret; } void usage(const char *name) -- http://www.hailfinger.org/

10 years, 7 months

1
1
0 0

bad flash ?

by Benjamin BELLEC

Hello, I have tried to flash the BIOS of my motherboard. It's a Gigabyte G33M-DS2R (ICH9R + SST SST25VF080B" (1024 KB)). [root@scarabee benjamin]# flashrom --version flashrom v0.9.0 (on Fedora 11 x86_64) Here is the log of the flash (my motherboard was previously in version F7) : flashrom --write ./G33MDS2R.F8 Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... OK. Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: [root@scarabee motherboard_bios_ga-g33m-ds2r_f8]# and I check the BIOS : [root@scarabee motherboard_bios_ga-g33m-ds2r_f8]# flashrom --verify ./G33MDS2R.F8 Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... OK. Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... FAILED at 0x00000000! Expected=0x00, Read=0x01 [root@scarabee motherboard_bios_ga-g33m-ds2r_f8]# and when I try to erase it : [root@scarabee benjamin]# flashrom --erase Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... OK. Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Erasing flash chip... FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x01 [root@scarabee benjamin]# I can post the entire log (--write --verbose) if you want. What can I do, is my BIOS really write or not ? Can I reboot ? Thanks for your time. Benjamin (from France)

10 years, 7 months

3
3
0 0

[PATCH] Documentation update

by Stefan Reinauer

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

10 years, 7 months

3
2
0 0

[PATCH] Add IDs for 44 new flash chips

by Carl-Daniel Hailfinger

Add IDs for 25 AMD chips, 8 Sharp chips, 11 Hynix chips and their variants. AM29DL400BB AM29DL400BT AM29DL800BB AM29DL800BT AM29F004BB AM29F004BT AM29F200BB AM29F200BT AM29F400BB AM29F400BT AM29F800BB AM29F800BT AM29LV002BB AM29LV002BT AM29LV004BB AM29LV004BT AM29LV008BB AM29LV008BT AM29LV080B AM29LV200BB AM29LV200BT AM29LV400BB AM29LV400BT AM29LV800BB AM29LV800BT HY29F002 HY29F040A HY29F080 HY29F400B HY29F400T HY29F800B HY29F800T HY29LV400B HY29LV400T HY29LV800B HY29LV800T LH28F008BJxxPB LH28F008BJxxPT LH28F008SA LH28F008SC LH28F800BVxxBTL LH28F800BVxxBV LH28F800BVxxTV LHF00L02 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-newids/flashchips.h =================================================================== --- flashrom-newids/flashchips.h (Revision 667) +++ flashrom-newids/flashchips.h (Arbeitskopie) @@ -39,20 +39,44 @@ #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ #define AMD_ID 0x01 /* AMD */ +#define AM_29DL400BT 0x0C +#define AM_29DL400BB 0x0F +#define AM_29DL800BT 0x4A +#define AM_29DL800BB 0xCB +#define AM_29F002BB 0x34 /* Same as Am29F002NBB */ +#define AM_29F002BT 0xB0 /* Same as Am29F002NBT */ +#define AM_29F004BB 0x7B +#define AM_29F004BT 0x77 +#define AM_29F016D 0xAD #define AM_29F010B 0x20 /* Same as Am29F010A */ -#define AM_29F002BT 0xB0 -#define AM_29F002BB 0x34 #define AM_29F040B 0xA4 #define AM_29F080B 0xD5 +#define AM_29F200BB 0x57 +#define AM_29F200BT 0x51 +#define AM_29F400BB 0xAB +#define AM_29F400BT 0x23 +#define AM_29F800BB 0x58 +#define AM_29F800BT 0xD6 +#define AM_29LV002BB 0xC2 +#define AM_29LV002BT 0x40 +#define AM_29LV004BB 0xB6 +#define AM_29LV004BT 0xB5 +#define AM_29LV008BB 0x37 +#define AM_29LV008BT 0x3E #define AM_29LV040B 0x4F -#define AM_29LV081B 0x38 -#define AM_29F016D 0xAD +#define AM_29LV080B 0x38 /* Same as Am29LV081B */ +#define AM_29LV200BB 0xBF +#define AM_29LV200BT 0x3B +#define AM_29LV800BB 0x5B /* Same as Am29LV800DB */ +#define AM_29LV400BT 0xB9 +#define AM_29LV400BB 0xBA +#define AM_29LV800BT 0xDA /* Same as Am29LV800DT */ #define AMIC_ID 0x7F37 /* AMIC */ #define AMIC_ID_NOPREFIX 0x37 /* AMIC */ #define AMIC_A25L40P 0x2013 #define AMIC_A29002B 0x0d -#define AMIC_A29002T 0x8c +#define AMIC_A29002T 0x8C /* Same as A290021T */ #define AMIC_A29040B 0x86 #define AMIC_A29400T 0xB0 /* Same as 294001T */ #define AMIC_A29400U 0x31 /* Same as A294001U */ @@ -194,16 +218,29 @@ #define MBM29LV800TA 0xDA /* Same as MBM29LV800TE */ #define HYUNDAI_ID 0xAD /* Hyundai */ +#define HY_29F400T 0x23 /* Same as HY_29F400AT */ +#define HY_29F800B 0x58 /* Same as HY_29F800AB */ +#define HY_29LV800B 0x5B +#define HY_29F040A 0xA4 +#define HY_29F400B 0xAB /* Same as HY_29F400AB */ +#define HY_29F002 0xB0 +#define HY_29LV400T 0xB9 +#define HY_29LV400B 0xBA +#define HY_29F080 0xD5 +#define HY_29F800T 0xD6 /* Same as HY_29F800AT */ +#define HY_29LV800T 0xDA #define IMT_ID 0x7F1F /* Integrated Memory Technologies */ #define IM_29F004B 0xAE #define IM_29F004T 0xAF #define INTEL_ID 0x89 /* Intel */ -#define I_82802AB 0xAD -#define I_82802AC 0xAC +#define I_82802AB 0xAD +#define I_82802AC 0xAC #define P28F001BXT 0x94 /* 28F001BX-T */ #define P28F001BXB 0x95 /* 28F001BX-B */ +#define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ +#define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ @@ -287,14 +324,20 @@ #define PMC_49FL004 0x6E #define SHARP_ID 0xB0 /* Sharp */ -#define SHARP_LHF00L04 0xCF +#define SHARP_LH28F008BJxxPT 0xEC +#define SHARP_LH28F008BJxxPB 0xED +#define SHARP_LH28F800BVxxBTL 0x4B +#define SHARP_LH28F800BVxxBV 0x4D +#define SHARP_LH28F800BVxxTV 0x4C +#define SHARP_LHF00L02 0xC9 /* Same as LHF00L06/LHF00L07 */ +#define SHARP_LHF00L04 0xCF /* Same as LHF00L03/LHF00L05 */ /* * Spansion was previously a joint venture of AMD and Fujitsu. * S25 chips are SPI. The first device ID byte is memory type and * the second device ID byte is memory capacity. */ -#define SPANSION_ID 0x01 /* Spansion */ +#define SPANSION_ID 0x01 /* Spansion, same ID as AMD */ #define SPANSION_S25FL016A 0x0214 /* @@ -336,13 +379,13 @@ #define SST_29SF040 0x13 #define SST_29VF040 0x14 #define SST_39SF010 0xB5 -#define SST_39SF020 0xB6 +#define SST_39SF020 0xB6 /* Same as 39SF020A */ #define SST_39SF040 0xB7 #define SST_39VF512 0xD4 #define SST_39VF010 0xD5 -#define SST_39VF020 0xD6 -#define SST_39VF040 0xD7 -#define SST_39VF080 0xD8 /* Same as SST_39LF080/39VF080/39VF088 */ +#define SST_39VF020 0xD6 /* Same as 39LF020 */ +#define SST_39VF040 0xD7 /* Same as 39LF040 */ +#define SST_39VF080 0xD8 /* Same as 39LF080/39VF080/39VF088 */ #define SST_49LF040B 0x50 #define SST_49LF040 0x51 #define SST_49LF020 0x61 @@ -351,7 +394,7 @@ #define SST_49LF080A 0x5B #define SST_49LF002A 0x57 #define SST_49LF003A 0x1B -#define SST_49LF004A 0x60 +#define SST_49LF004A 0x60 /* Same as 49LF004B */ #define SST_49LF008A 0x5A #define SST_49LF004C 0x54 #define SST_49LF008C 0x59 @@ -389,14 +432,14 @@ #define ST_M50FW080 0x2D #define ST_M50FW016 0x2E #define ST_M50LPW116 0x30 -#define ST_M29F002B 0x34 -#define ST_M29F002T 0xB0 /* M29F002T / M29F002NT */ -#define ST_M29F040B 0xE2 +#define ST_M29F002B 0x34 /* Same as M29F002BB */ +#define ST_M29F002T 0xB0 /* Same as M29F002BT/M29F002NT/M29F002BNT */ +#define ST_M29F040B 0xE2 /* Same as M29F040 */ #define ST_M29F080 0xF1 #define ST_M29F200BT 0xD3 #define ST_M29F200BB 0xD4 -#define ST_M29F400BT 0xD5 -#define ST_M29F400BB 0xD6 +#define ST_M29F400BT 0xD5 /* Same as M29F400T */ +#define ST_M29F400BB 0xD6 /* Same as M29F400B */ #define ST_M29F800DB 0x58 #define ST_M29F800DT 0xEC #define ST_M29W010B 0x23 @@ -427,8 +470,8 @@ #define W_25X32 0x3016 #define W_25X64 0x3017 #define W_29C011 0xC1 -#define W_29C020C 0x45 -#define W_29C040P 0x46 +#define W_29C020C 0x45 /* Same as W29C020 */ +#define W_29C040P 0x46 /* Same as W29C040 */ #define W_29EE011 0xC1 #define W_39L020 0xB5 #define W_39L040 0xB6 -- http://www.hailfinger.org/

10 years, 7 months

2
3
0 0

[PATCH] ICH6-ICH10 flash decode debugging

by Carl-Daniel Hailfinger

Add ICH6,ICH7,ICH8,ICH9,ICH10 FWH IDSEL settings and flash decode settings to the debug output. This can help debug cases where the BIOS does not set up a correct flash decode for the given flash size. The Intel docs state that the decode applies to FWH and SPI flash. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich6_fwh_idsel_debug/chipset_enable.c =================================================================== --- flashrom-ich6_fwh_idsel_debug/chipset_enable.c (Revision 667) +++ flashrom-ich6_fwh_idsel_debug/chipset_enable.c (Arbeitskopie) @@ -192,11 +192,43 @@ static int enable_flash_ich_4e(struct pci_dev *dev, const char *name) { + /* + * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and + * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and + * FB_DEC_EN2. + */ return enable_flash_ich(dev, name, 0x4e); } static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) { + uint32_t fwh_conf; + int i; + + /* Ignore all legacy ranges below 1 MB. */ + /* FWH_SEL1 */ + fwh_conf = pci_read_long(dev, 0xd0); + for (i = 7; i >= 0; i--) + printf_debug("0xff%02x/0xff%02x FWH IDSEL: 0x%x, ", + i * 0x8 + 0xc0, i * 0x8 + 0x80, + (fwh_conf >> (i * 4)) & 0xf); + /* FWH_SEL2 */ + fwh_conf = pci_read_word(dev, 0xd4); + for (i = 3; i >= 0; i--) + printf_debug("0xff%02x/0xff%02x FWH IDSEL: 0x%x, ", + i * 0x10 + 0x40, i * 0x10, + (fwh_conf >> (i * 4)) & 0xf); + /* FWH_DEC_EN1 */ + fwh_conf = pci_read_word(dev, 0xd8); + for (i = 7; i >= 0; i--) + printf_debug("0xff%02x/0xff%02x FWH decode %sabled, ", + i * 0x8 + 0xc0, i * 0x8 + 0x80, + (fwh_conf >> (i + 0x8)) & 0x1 ? "en" : "dis"); + for (i = 3; i >= 0; i--) + printf_debug("0xff%02x/0xff%02x FWH decode %sabled, ", + i * 0x10 + 0x40, i * 0x10, + (fwh_conf >> i) & 0x1 ? "en" : "dis"); + printf_debug("\n"); return enable_flash_ich(dev, name, 0xdc); } -- http://www.hailfinger.org/

10 years, 8 months

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[commit] r669 - trunk

by svn＠flashrom.org

Author: stepan Date: 2009-07-30 15:32:26 +0200 (Thu, 30 Jul 2009) New Revision: 669 Modified: trunk/README trunk/flashrom.8 trunk/flashrom.c trunk/pcidev.c Log: The project's new home is flashrom.org now. Change all occurences in the source code and documentation accordingly. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/README =================================================================== --- trunk/README 2009-07-30 13:30:17 UTC (rev 668) +++ trunk/README 2009-07-30 13:32:26 UTC (rev 669) @@ -122,5 +122,5 @@ The official flashrom website is: - http://coreboot.org/Flashrom + http://www.flashrom.org/ Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-07-30 13:30:17 UTC (rev 668) +++ trunk/flashrom.8 2009-07-30 13:32:26 UTC (rev 669) @@ -133,7 +133,7 @@ Same as .BR \-\-list\-supported , but outputs the supported hardware in MediaWiki syntax, so that it can be -easily pasted into the wiki page at http://coreboot.org/Flashrom. +easily pasted into the wiki page at http://www.flashrom.org/. .TP .B "\-p, \-\-programmer <name>" Specify the programmer device. Currently supported are: @@ -217,9 +217,9 @@ (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. .SH BUGS Please report any bugs at -.BR http://tracker.coreboot.org/trac/coreboot/newticket "," -or on the coreboot mailing list -.RB "(" http://coreboot.org/Mailinglist ")." +.BR http://www.flashrom.org/trac/flashrom/newticket "," +or on the flashrom mailing list +.RB "(" http://www.flashrom.org/mailman/listinfo/flashrom ")." .SH LICENCE .B flashrom is covered by the GNU General Public License (GPL), version 2. Some files are Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-07-30 13:30:17 UTC (rev 668) +++ trunk/flashrom.c 2009-07-30 13:32:26 UTC (rev 669) @@ -780,7 +780,7 @@ printf(" WRITE"); printf("\n"); } - printf("Please email a report to flashrom(a)coreboot.org if any " + printf("Please email a report to flashrom(a)flashrom.org if any " "of the above operations\nwork correctly for you with " "this flash part. Please include the flashrom\noutput " "with the additional -V option for all operations you " Modified: trunk/pcidev.c =================================================================== --- trunk/pcidev.c 2009-07-30 13:30:17 UTC (rev 668) +++ trunk/pcidev.c 2009-07-30 13:32:26 UTC (rev 669) @@ -51,7 +51,7 @@ if (devs[i].status == PCI_NT) { printf("===\nThis PCI device is UNTESTED. Please " "report the 'flashrom -p xxxx' output \n" - "to flashrom(a)coreboot.org if it works " + "to flashrom(a)flashrom.org if it works " "for you. Thank you for your help!\n===\n"); }

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flashrom July 2009