February 2021 - flashrom - mail.coreboot.org

Adding write protect/lock support to flashrom
by ln2＠mailo.com Oct. 18, 2021

Oct. 18, 2021

Hi all, I would like to see the following feature added to flashrom: https://github.com/flashrom/flashrom/issues/185 If someone implemented it, would the idea (at least) be accepted? Is anyone interested in implementing it and claiming the $100 bounty? Text of the issue, for people too lazy to click: Some chips require certain bits (and similar features) be set before the hardware write-protect pins can be used. Flashrom doesn't currently support setting these bits, which makes it impossible to e.g hardware write-protect a BIOS chip after flashing Coreboot. I would like to see Flashrom add support for this. Attached is a patch which was written by someone else (they can identify themselves if they like) to toggle the relevant bits for a particular flash chip, each time flashrom is run, and tell the user what's going on. Your task, if you want to claim the bounty, is to: 1- Add some UI sugar so that the user can choose to set the appropriate bits (or not), and any other "features" needed to enable hardware write-protect, via the command line 2- Ensure the necessary bits and features can be set for a specified set of chips (see below), so Flashrom supports hardware write protect for at least all of the listed chips, and 3- Get your patch accepted and merged (it may be wise to first check with the maintainers that they are willing to add this feature) using Gerrit or the mailing list as per the official process If $100 isn't enough to make this attractive, I am open to increasing the bounty. I am also happy to escrow it if need be. Payment will be in Bitcoin.

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flashrom on NetBSD 8 and apu2?
by Greg Troxel April 3, 2021

April 3, 2021

I have a PC Engines apu2d4 running NetBSD 8 (amd64), and would like to update coreboot/etc. on it. I searched the list (perhaps not well) and didn't find any reports of success, although I realize things are generally expected to work so success might well go unreported. I am using flashrom 1.1 as built from pkgsrc. I was able to read the existing bios without issues as: flashrom --programmer internal -r 20200301-readflash.rom Before I try to write, I am wondering if anyone has successfully done an apu2 bios update with flashrom under NetBSD 8 amd64? (I have a debricking adaptor (spi1a) and will prepare a Linux flashing image on USB before trying myself, whether I not a get a report of success.) Thanks, Greg

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Flashrom & Serprog Question
by egeebt00＠gmail.com March 2, 2021

March 2, 2021

Hello again. Posted this question in irc, but had to disconnect, thats why i ask here. I build Urja Rannikko's atmega644 programmer and used it with flashrom 0.9.9 on windows. If i do not connect a flash chip (only parallel flash chips here to test) to the programmer i get the messages that bus mode parallel and spi are on (lpc and hw off). When i connect a SST39VF040 to the programmer and execute flashrom the parallel mode is changed to off, so only spi is on. Can i force the programmer / flashrom to check only for flash chips in parallel mode (with a parameter e.g.)? I did notice, that i had the wrong jumper position set for the flash chip (5V instead of 3,3V). Is it possible that this is the reason why flashrom switches to spi? I'm pretty sure that the flash chip is dead now, but i have two more of this type :). Hope someone can help.

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About bios flash
by Aurelijus Gogas March 2, 2021

March 2, 2021

Hallow, Thanks for your work (flashrom). In hardware list there is w25q32, but mine is BV. Flashrom can not detect my chip. Is it not supported or i am doing something wrong? I wired like example in tutorial. I have arduino mega2560. What i can do? Thanks for help. With Best Regards Aurimas ⁣Get BlueMail for Android

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error bios
by edvaldo silva March 2, 2021

March 2, 2021

Found GigaDevice flash chip "GD25Q64(B)" (8192 kB, SPI) on ch341a_spi. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... FAILED at 0x00004500! Expected=0x45, Found=0xff, failed byte count from 0x00000000-0x007fffff: 0x156b2 Your flash chip is in an unknown state. Att, Edvaldo Silva mailto:edvaldo.set@zohomail.com +55 12 9 8209 6114

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Verifying flash failed
by Nathaniel King March 2, 2021

March 2, 2021

Hi, I have successfully erased and write the chip but it cannot verify it. When I try to boot it it doesn't even boot, fan spin on for a second and then off. I am flashing my t440p. I hope I have given you enough information. Thanks, Nathaniel

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Error on Yuna
by Flynn Price March 2, 2021

March 2, 2021

Hi, can you please see the error below? Am i safe to reboot? Previously it said the flash was in an unknown state and to not reboot. Thanks! Erasing and writing flash chip... 0x420000-0x427fff: EInvalid OPCODE 0x06, will not execute. spi_write_cmd failed during command execution at address 0x420000 ERASE_FAILED FAILED! Uh oh. Erase/write failed. Checking if anything changed. Reading current flash chip contents... 000000-0x7fffff:R done. Good, writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks!

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[PATCH] Add support for GD25LQ256D
by Drew Fustini Feb. 28, 2021

Feb. 28, 2021

Add support for GD25LQ256D [1]. I have tested both reading and writing complete ROM to this device using FT2232H (Tigard board) [2] connected to the GD25LQ256D on the BeagleV dev board [3]. [1] https://www.gigadevice.com/flash-memory/gd25lq256d/ [2] https://github.com/tigard-tools/tigard [3] https://beagleboard.org/beaglev Cc: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Drew Fustini <drew(a)beagleboard.org> --- Thanks very much to icon (Nico Huber) on #flashrom for the assistance! flashchips.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ flashchips.h | 1 + 2 files changed, 49 insertions(+) diff --git a/flashchips.c b/flashchips.c index 6d94a1252aad..55ccac642ad7 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6669,6 +6669,54 @@ const struct flashchip flashchips[] = { .voltage = {2700, 3600}, }, + { + .vendor = "GigaDevice", + .name = "GD25LQ256D", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LQ256D, + .total_size = 32768, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp3_srwd, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 2000}, + }, + + { .vendor = "GigaDevice", .name = "GD25Q32(B)", diff --git a/flashchips.h b/flashchips.h index a85fa6a6bf71..2340d92a917f 100644 --- a/flashchips.h +++ b/flashchips.h @@ -398,6 +398,7 @@ #define GIGADEVICE_GD25LQ32 0x6016 #define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster) */ #define GIGADEVICE_GD25LQ128CD 0x6018 +#define GIGADEVICE_GD25LQ256D 0x6019 #define GIGADEVICE_GD25WQ80E 0x6514 #define GIGADEVICE_GD29GL064CAB 0x7E0601 -- 2.25.1

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How do i register to use freenode #flashrom?
by julian Feb. 25, 2021

Feb. 25, 2021

And avoid * #flashrom :Cannot send to nick/channel

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VL805 Flash SPI Bus Programmer Support
by Neil Armstrong Feb. 22, 2021

Feb. 22, 2021

Hi All, Following Carl-Daniel Hailfinger's work on supporting the VL805 PCIe-USB3 Controller SPI bus at [1], I pushed a cleaned, tested and fixed version on gerrit. I had someone successfully testing support on it's own HW, but now it lacks proper review. I'll be happy to fix the code to have it merged in the flashrom tree. Best Regards, Neil [1] https://www.mail-archive.com/flashrom@flashrom.org/msg14389.html [2] https://review.coreboot.org/c/flashrom/+/50264 -- Neil Armstrong Embedded Linux Software Engineer BayLibre - At the Heart of Embedded Linux www.baylibre.com

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