flashrom July 2021

flashrom@flashrom.org

20 participants
13 discussions

Adding write protect/lock support to flashrom
by ln2＠mailo.com 18 Oct '21

18 Oct '21

Hi all, I would like to see the following feature added to flashrom: https://github.com/flashrom/flashrom/issues/185 If someone implemented it, would the idea (at least) be accepted? Is anyone interested in implementing it and claiming the $100 bounty? Text of the issue, for people too lazy to click: Some chips require certain bits (and similar features) be set before the hardware write-protect pins can be used. Flashrom doesn't currently support setting these bits, which makes it impossible to e.g hardware write-protect a BIOS chip after flashing Coreboot. I would like to see Flashrom add support for this. Attached is a patch which was written by someone else (they can identify themselves if they like) to toggle the relevant bits for a particular flash chip, each time flashrom is run, and tell the user what's going on. Your task, if you want to claim the bounty, is to: 1- Add some UI sugar so that the user can choose to set the appropriate bits (or not), and any other "features" needed to enable hardware write-protect, via the command line 2- Ensure the necessary bits and features can be set for a specified set of chips (see below), so Flashrom supports hardware write protect for at least all of the listed chips, and 3- Get your patch accepted and merged (it may be wise to first check with the maintainers that they are willing to add this feature) using Gerrit or the mailing list as per the official process If $100 isn't enough to make this attractive, I am open to increasing the bounty. I am also happy to escrow it if need be. Payment will be in Bitcoin.

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Public Key
by Aleks Ozolins 17 Aug '21

17 Aug '21

Hi there! Downloading a tarball off website and trying to verify signature. Can you point me towards the public key or fingerprint? Thank you! -- Aleks Ozolins m:973.464.5242 aleks(a)aleksozolins.com https://www.aleksozolins.com

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SMM BIOS protection Enabled!
by Munduru Avinash (Europe - iDEAS-ER&D) 28 Jul '21

28 Jul '21

HI, I am working on Intel Denverton c3558 processor and bootloader I am using is Coreboot. For this flashrom utility support is not given. But some how I added this utility. When I tried running this utility. I am getting the following output. ******************************************************************************************************************************** root@CMM2:/mnt# flashrom -p internal -w coreboot-working.rom flashrom v1.2 on Linux 4.19.198-cmm2 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Cannot open file stream for /dev/mtd0 coreboot table found at 0x7f76f000. Found chipset "Intel Denverton". Enabling flash write... Warning: BIOS region SMM protection is enabled! Warning: Setting Bios Control at 0xdc from 0xab to 0x89 failed. New value is 0xab. SPI Configuration is locked down. PR0: Warning: 0x00000000-0x00000fff is read-only. PR1: Warning: 0x00000000-0x00000fff is read-only. PR2: Warning: 0x00000000-0x00000fff is read-only. PR3: Warning: 0x00000000-0x00000fff is read-only. PR4: Warning: 0x00000000-0x00000fff is read-only. At least some flash regions are write protected. For write operations, you should use a flash layout and include only writable regions. See manpage for more details. Enabling hardware sequencing because some important opcode is locked. OK. Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Reading old flash chip contents... Transaction error between offset 0x00ccb000 and 0x00ccb03f (= 0x00ccb000 + 63)! FAILED. root@CMM2:/mnt# The Flash chip I am having is N25Q128..3E but it is recognizing as Opaque flash chip. Could you please suggest a solution for this. Regards, Avinash. Sensitivity: Internal & Restricted 'The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments. WARNING: Computer viruses can be transmitted via email. The recipient should check this email and any attachments for the presence of viruses. The company accepts no liability for any damage caused by any virus transmitted by this email. www.wipro.com'

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Unknown SPI Chip for CH341A
by Georg Urff 28 Jul '21

28 Jul '21

Hello, the following Chip is not working with latest verion of flashrom on Ubuntu and CH341A: Issi IS25WP080 DNLE Found Generic flash chip "unkown SPI chip (RDID)" (0kb, SPI) on ch341a_spi This flash part has status NOT WORKING for operations: PROBE READ ERASE WRITE Cheers Georg Urff -- Diese E-Mail wurde von Avast Antivirus-Software auf Viren geprüft. https://www.avast.com/antivirus

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Full UEFI firmware install error on AKEMI
by David Horner 27 Jul '21

27 Jul '21

I received the following errors when attempting to install full UEFI firmware. The statements about rebooting conflict with each other too. The first says that a reboot can be done, the second says do not reboot in CAPS. I believe I followed the instructions correctly, all of the checks matched the instructions. Thank you in advance for help with what to do next. Please note that I am not including the many lines that preceded the error lines below. Dave ** Device: Lenovo Ideapad Flex 5 Chromebook (AKEMI) ** Platform: Intel CometLake ** Fw Type: Stock ChromeOS w/RW_LEGACY ** Fw Ver: Google_Akemi.12672.375.0 (12/16/2020) ** Fw WP: Disabled ==================================================== HSFC used for block erasing: HSFC: FGO=1, HSFC=3, WET=0, FDBC=63, SME=0 Transaction error between offset 0x00ad0000 and 0x00ad0fff (= 0x00ad0000 + 4095)! HSFS: FDONE=1, FCERR=1, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=0, FDOPSS=1, FDV=1, FLOCKDN=1 HSFC: FGO=0, HSFC=3, WET=0, FDBC=63, SME=0 ERASE_FAILED FAILED! Uh oh. Erase/write failed. Checking if anything changed. Reading current flash chip contents... 000000-0xffffff:R Reading 16777216 bytes starting at 0x000000. ignoring error when reading 0x0-0xffffff done. Good, writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. FAILED Restoring PCI config space for 00:1f:5 reg 0xdc restore_power_management: Re-enabling power management. An error occurred flashing the Full ROM firmware. DO NOT REBOOT! Press [Enter] to return to the main menu.

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flashrom -p internal does not work on HP 8200 SFF Elite
by karmo 24 Jul '21

24 Jul '21

Hi Please take a look at the error log. PC is running HP BIOS J01_0233.bin, ME cleaned, HAP bit Set (me_cleaner.py). Chipset: Intel Q67. BIOS Chip is Macronix MX25L6406E. BB and FDO Jumpers are both set on the Mainboard. Can you help me, please? Thank you very much... A. P.

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all 1's - parity violation - No EEPROM/flash device found - compare_id: id1 0xff, id2 0xffff for *every* device tested
by James Feeney 17 Jul '21

17 Jul '21

Where to look for a cause? I have an only partially booting coreboot firmware image on a Geminilake Chromebook, apparently with a bad payload, but the flash device is obviously being read on boot, as can be seen on the AP console. Short version: Chromebook boot can read the flash device, but flashrom, through SuzyQable, only reads all "1's". Have a sparkfun SuzyQable connected to an Arch Linux box, and to the Chromebook. Have the desired result after running on the Cr50 console: > ccd reset factory > ccd testlab enable > ccd open Previously running flashrom from the stock ChromeOS would give 'Found GigaDevice flash chip "GD25LQ128C/GD25LQ128D"'. I have flashrom from both: git clone https://chromium.googlesource.com/chromiumos/third_party/flashrom WARNERROR=no CONFIG_MEC1308=no CONFIG_ENE_LPC=no make and git clone https://chromium.googlesource.com/chromiumos/platform/standalone-hdctools flashrom install These appear to both act exactly the same. Then: sudo ./flashrom -V -p raiden_debug_spi:target=AP results in "No EEPROM/flash device found", where: $ sudo ./flashrom -V -p raiden_debug_spi:target=AP |sed -n 's/.*$compare.*$/\1/p'|sort|uniq compare_id: id1 0xff, id2 0xff compare_id: id1 0xff, id2 0xffff From running flashrom, the Cr50 console says: [10398.332186 enable_spi_pinmux: AP] [10398.445490 usb_spi_board_disable] [10399.512358 AP UART on] [10399.514036 CCD state: UARTAP+TX UARTEC+TX I2C SPI USBEC+TX] [10399.728811 deferred_tpm_rst_isr] [10399.730025 AP on] [10399.730757 tpm_reset_request(0, 0)] [10399.731775 tpm_reset_now(0)] [10399.735335 tpm_init] tpm_manufactured: manufactured [10399.737601 tpm_reset_now: done] [10402.488852 PinWeaver: Loading Tree!] [10402.511275 PinWeaver: Loaded Tree. restart_count = 88] [10402.513121 Skipping commit] [10402.738718 Committing NVMEM changes.] This causes the Chromebook to boot, so then: [10408.218302 power button pressed] [10408.355704 tpm_rst_asserted] [10409.356714 AP off] [10418.538157 AP UART off] [10418.540362 CCD state: UARTEC+TX I2C SPI USBEC+TX] I don't know whether or not there should be a report of "usb_spi_board_enable" being called, but it is conspicuously not seen. If I understand, it appears as if flashrom reads and caches the flash device ID, but is just seeing all "1's". So - where is the problem? ... the flash device? the "pinmux" accessing the flash? the SPI channel? the USB channel? the Cr50? the raiden_debug_spi driver? some Cr50 configuration variable? some nasty hardware problem? I did run-across this odd thread: https://groups.google.com/a/chromium.org/g/chromium-os-discuss/c/yFevUZz9aac where running flashrom first gives "No EEPROM/flash device found", but subsequently reports, in that case, "Found Winbond flash chip "W25Q256JV_M" (32768 kB, SPI) on raiden_debug_spi." But, the reason for the different consecutive responses from flashrom were not explored there. Any thoughts about why the boot process can read the flash device, while flashrom only reads "1's" for the device ID? I did try running flashrom while specifying the device and forcing a read, but again, it just sees all "1's". Thanks James

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Flashrom asked me to do this
by havsfrun＠topchan.eu 17 Jul '21

17 Jul '21

flashrom v1.2 on Linux 5.13.1-1-default (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found SST flash chip "SST25VF016B" (2048 kB, SPI) on ch341a_spi. Reading old flash chip contents... done. Erasing and writing flash chip... FAILED at 0x00000000! Expected=0xff, Found=0x4e, failed byte count from 0x00000000-0x00000fff: 0xfb8 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x00000003! Expected=0xff, Found=0x7f, failed byte count from 0x00000000-0x00007fff: 0x1e76 ERASE FAILED! Reading current flash chip contents... cb_in: error: LIBUSB_TRANSFER_TIMED_OUT ch341a_spi_spi_send_command: Failed to read 4100 bytes libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 libusb: warning [handle_timeout] async cancel failed -5 Can't read anymore! Aborting. FAILED! Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... done. Apparently at least some data has changed. Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks!

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FAILED: apu2e4
by Stephen Hladysh 17 Jul '21

17 Jul '21

flashrom -w /tmp/apu2_v4.14.0.1.rom -p internal flashrom v1.2 on FreeBSD 12.2-STABLE (amd64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 4, resolution: 2ns). coreboot table found at 0xcfec1000. Found chipset "AMD FCH". Enabling flash write... OK. Found Winbond flash chip "W25Q64.V" (8192 kB, SPI) mapped at physical address 0x00000000ff800000. Reading old flash chip contents... done. Erasing and writing flash chip... FAILED at 0x0000e000! Expected=0xff, Found=0x00, failed byte count from 0x0000e000-0x0000efff: 0x217 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Erase/write done. Verifying flash... FAILED at 0x00000000! Expected=0x2f, Found=0xff, failed byte count from 0x00000000-0x007fffff: 0x101cb1 Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF!

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Unknown programmer "ft2232_spi"
by Michael Leukert - AMPEGON 15 Jul '21

15 Jul '21

Hello! Do you have any idea why our flashrom v0.9.9 won't accept ft2232_spi as a programmer? We want to use flashrom for our ft2232_spi devices and the website flashrom.org/Flashrom/0.9.9/Supported_Hardware claims that flashrom v0.9.9 supports ft2232_spi. However, for some reason it just won't accept ft2232_spi as a programmer: - flashrom -p ft2232_spi flashrom v0.9.9-rc1-r1942 on Linux 4.15.0-45-generic (i686) flashrom is free software, get the source code at https://flashrom.org Error: Unknown programmer "ft2232_spi". Valid choices are: internal, dummy, nic3com, nicrealtek, gfxnvidia, drkaiser, satasii, atavia, it8212, serprog, buspirate_spi, dediprog, rayer_spi, pony_spi, nicintel, nicintel_spi, nicintel_eeprom, ogp_spi, satamv, linux_spi, pickit2_spi, ch341a_spi. Please run "flashrom --help" for usage info. Surprisingly, even the man page claims that ft2232_spi is supported: - man flashrom ... -p, --programmer <name>[:parameter[,parameter[,parameter]]] Specify the programmer device. This is mandatory for all operations involving any chip access (probe/read/write/...). Currently supported are: ... * ft2232_spi (for SPI flash ROMs attached to an FT2232/FT4232H/FT232H family based USB SPI programmer), including the DLP Design DLP-USB1232H, FTDI FT2232H Mini-Module, FTDI FT4232H Mini-Module, openbiosprog-spi, Amontec JTAGkey/JTAGkey-tiny/JTAGkey-2, Dangerous Prototypes Bus Blaster, Olimex ARM-USB-TINY/-H, Olimex ARM-USB-OCD/-H, TIAO/DIYGADGET USB Multi-Protocol Adapter (TUMPA), TUMPA Lite, GOEPEL PicoTAP and Google Servo v1/v2. ... This is how we installed it: - sudo apt install flashrom Reading package lists... Done Building dependency tree Reading state information... Done The following NEW packages will be installed: flashrom 0 upgraded, 1 newly installed, 0 to remove and 0 not upgraded. Need to get 169 kB of archives. After this operation, 868 kB of additional disk space will be used. Get:1 http://ch.archive.ubuntu.com/ubuntu xenial/universe i386 flashrom i386 0.9.9~rc1+r1942-1 [169 kB] Fetched 169 kB in 0s (1'116 kB/s) Selecting previously unselected package flashrom. (Reading database ... 165415 files and directories currently installed.) Preparing to unpack .../flashrom_0.9.9~rc1+r1942-1_i386.deb ... Unpacking flashrom (0.9.9~rc1+r1942-1) ... Processing triggers for man-db (2.7.5-1) ... Setting up flashrom (0.9.9~rc1+r1942-1) ... This is our system: - cat /etc/lsb-release DISTRIB_ID=Ubuntu DISTRIB_RELEASE=16.04 DISTRIB_CODENAME=xenial DISTRIB_DESCRIPTION="Ubuntu 16.04.6 LTS" - uname -m i686 We don't understand why our flashrom won't accept ft2232_spi or how to proceed. And would appreciate any assistance, if you have the resources to assist or even just point us in the right direction here we can fix this ourselves. Freundliche Grüsse | Best regards, Michael Leukert | Software Developer R&D-ES Direct +41 58 710 4469 michael.leukert(a)ampegon.com Ampegon Power Electronics AG Kreuzweg 11 | 5400 Baden, Switzerland Tel.+ 41 58 710 44 00 | Fax +41 58 710 44 01 info(a)ampegon.com | ampegon.com MWST Nr. CHE-310.342.455 MWST | UID: CHE-310.342.455 Follow Ampegon's latest news online via our website<https://ampegon.com/news/> or LinkedIn<https://ch.linkedin.com/company/ampegon> group

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flashrom July 2021