September 2009 - flashrom - mail.coreboot.org

#1: flashRom doesn't work on MotherBoard with ICH9 + MP2532
by flashrom Oct. 26, 2010

Oct. 26, 2010

#1: flashRom doesn't work on MotherBoard with ICH9 + MP2532 --------------------------------------------------+------------------------- Reporter: annyvonne.le_coq@… | Owner: hailfinger Type: defect | Status: new Priority: major | Milestone: flashrom 0.9.1 Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | --------------------------------------------------+------------------------- Hi all, I have a mother board equipped with ICH9 chipset and M25P32 flash device. I can't use flashrom to re-program my BIOS. 1) The ICH9 is not recognized. So, I add its device ID (2910) in chipset_enable.c file. 2) Then, M25P32 flash device is recognized, but OPCODE 06 is not in the list OPCODESS OS_ST_M25P. ich_spi_command try to find the command 06 in the list, The list contains only following values: 2, 3, 216, 5, 171, 1, 159, 199. The M25P32 has been tested with flashrom. So, I imagine that the problem is due to the caller. Have you got an idea about this issue. Thanks Anne -- Ticket URL: <http://www.flashrom.org/trac/flashrom/ticket/1> flashrom <http://www.flashrom.org/>

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[PATCH] new windows port
by Stefan Reinauer June 4, 2010

June 4, 2010

Hi, I separated the direct io access code from the flashrom changes, to make this code easily available for the other coreboot utilities, too. The remaining windows patch is rather small. I'll clean up the directio code some more and make a release asap. Best regards, Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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[PATCH] Check if an erase is needed to write
by Carl-Daniel Hailfinger March 8, 2010

March 8, 2010

For optimal partial reflashing, we have to find out which parts of the chip can be written without erase. For that, the only criterion (except a limit on the number of writes for very old chips) is whether the write will only clear bits (set them to 0). If (current&new==new) we can skip the erase. If any bit would have to be set to 1, we need to erase. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-need_erase/flash.h =================================================================== --- flashrom-need_erase/flash.h (Revision 725) +++ flashrom-need_erase/flash.h (Arbeitskopie) @@ -455,6 +455,7 @@ int max(int a, int b); int check_erased_range(struct flashchip *flash, int start, int len); int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, char *message); +int need_erase(uint8_t *have, uint8_t *want, int len); char *strcat_realloc(char *dest, const char *src); #define OK 0 Index: flashrom-need_erase/flashrom.c =================================================================== --- flashrom-need_erase/flashrom.c (Revision 725) +++ flashrom-need_erase/flashrom.c (Arbeitskopie) @@ -379,6 +379,26 @@ return ret; } +/** + * Check if the buffer have can be programmed to the content of want without + * erasing. This is only possible if no bit has to be set to 1. + * + * @have buffer with current content + * @want buffer with desired content + * @len length of the verified area + * @return 0 if no erase is needed, >0 otherwise + */ +int need_erase(uint8_t *have, uint8_t *want, int len) +{ + int failcount = 0; + int i; + + for (i = 0; i < len; i++) + if ((have[i] & want[i]) != want[i]) + failcount++; + return failcount; +} + struct flashchip *probe_flash(struct flashchip *first_flash, int force) { struct flashchip *flash; -- http://www.hailfinger.org/

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[patch] add intel_piix4_gpo_set()
by Luc Verhaegen Dec. 14, 2009

Dec. 14, 2009

This is code from a an old board enable that i sent in 3 weeks ago. This board enable was not necessary (as flashing worked just fine without it too). But this function was also used to clean up the board enable for the epox ep bx3. I have tracked down the person for whom i wrote this board enable 2 years ago: irc user nyu, aka Robert Millan. Robert, can you verify that this code is not a regression for you? Uwe, in the original mail thread (http://www.coreboot.org/pipermail/coreboot/2009-June/049789.html) you had several suggestions. I have taken over unsigned int and the bitshift, but i do mot like to put "PIIX4{,E,M}" everywhere. "PIIX4{,E,M}" all over clutters up the place, and i fear that printing this to the user will generate more confusion than it will ever remove. Instead i have adjusted the initial function comment to mention this so that developers can rest assured in future that this will also be valid for their future board enables. Luc Verhaegen.

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[Patch] Shuttle AK31
by Luc Verhaegen Dec. 14, 2009

Dec. 14, 2009

Resending this patch to the newly formed flashrom ml. Ron already kindly acked this patch. Mateusz, the owner of this board gave me a brief comment on irc stating that it didn't work. Which is also the last i heard from him. Mateusz, get back to us and get us at least the flashrom output. Luc Verhaegen.

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non-working board report for Asrock K7S41GX with flashrom r711
by Putlinuxonit Nov. 28, 2009

Nov. 28, 2009

Hi, Just want to report a non-working board - the Asrock K7S41GX, tested with flashrom r711 and superiotool r4623. first some brief details ... Board: Asrock K7S1GX Bios Vendor: AMI Bios Version: P1.90 root@ubuntu:~# lspci 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 741/741GX/M741 Host (rev 03) 00:01.0 PCI bridge: Silicon Integrated Systems [SiS] SiS AGP Port (virtual PCI-to-PCI bridge) 00:02.0 ISA bridge: Silicon Integrated Systems [SiS] SiS963 [MuTIOL Media IO] (rev 25) 00:02.1 SMBus: Silicon Integrated Systems [SiS] SiS961/2 SMBus Controller 00:02.5 IDE interface: Silicon Integrated Systems [SiS] 5513 [IDE] 00:02.7 Multimedia audio controller: Silicon Integrated Systems [SiS] AC'97 Sound Controller (rev a0) 00:03.0 USB Controller: Silicon Integrated Systems [SiS] USB 1.1 Controller (rev 0f) 00:03.1 USB Controller: Silicon Integrated Systems [SiS] USB 1.1 Controller (rev 0f) 00:03.2 USB Controller: Silicon Integrated Systems [SiS] USB 2.0 Controller 00:04.0 Ethernet controller: Silicon Integrated Systems [SiS] SiS900 PCI Fast Ethernet (rev 90) 01:00.0 VGA compatible controller: Silicon Integrated Systems [SiS] 661/741/760 PCI/AGP or 662/761Gx PCIE VGA Display Adapter flashrom v0.9.1-r711 No coreboot table found. This chipset supports the following protocols: Non-SPI. WARNING: No chipset found. Flash detection will most likely fail. Calibrating delay loop... OK. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. root@ubuntu:~# ./superiotool/superiotool superiotool r4623 Found Winbond W83697HF/F/HG (id=0x60, rev=0x12) at 0x2e Cheers, -- Udu Ogah .~~~~~~~~~~.

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[PATCH] Totally generic SPI chip match
by Carl-Daniel Hailfinger Nov. 20, 2009

Nov. 20, 2009

If a chip is not on the RDID generic vendor list nor on the REMS specific ID list, flashrom will claim that no chip is there. Handle these cases gracefully. flashrom will ignore generic matches if a specific chip was found, so this will have no impact on supported chips, but help a lot for a first quick analysis by the user or developer. The only drawback is that unknown chips may be recognized multiple times until they are added to flashchips.[ch]. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_totally_generic_probe/flashchips.c =================================================================== --- flashrom-spi_totally_generic_probe/flashchips.c (Revision 664) +++ flashrom-spi_totally_generic_probe/flashchips.c (Arbeitskopie) @@ -3167,5 +3167,32 @@ .read = NULL, }, + { + .vendor = "Generic", + .name = "unknown SPI chip (RDID)", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = GENERIC_DEVICE_ID, + .total_size = 0, + .page_size = 256, + .tested = TEST_BAD_PREW, + .probe = probe_spi_rdid, + .erase = NULL, + .write = NULL, + }, + { + .vendor = "Generic", + .name = "unknown SPI chip (REMS)", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = GENERIC_DEVICE_ID, + .total_size = 0, + .page_size = 256, + .tested = TEST_BAD_PREW, + .probe = probe_spi_rems, + .erase = NULL, + .write = NULL, + }, + { NULL } }; Index: flashrom-spi_totally_generic_probe/flashchips.h =================================================================== --- flashrom-spi_totally_generic_probe/flashchips.h (Revision 664) +++ flashrom-spi_totally_generic_probe/flashchips.h (Arbeitskopie) @@ -34,6 +34,7 @@ * SPI parts have 16-bit device IDs if they support RDID. */ +#define GENERIC_MANUF_ID 0xffff /* Check if there is a vendor ID */ #define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */ #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ Index: flashrom-spi_totally_generic_probe/spi.c =================================================================== --- flashrom-spi_totally_generic_probe/spi.c (Revision 664) +++ flashrom-spi_totally_generic_probe/spi.c (Arbeitskopie) @@ -274,6 +274,11 @@ GENERIC_DEVICE_ID == flash->model_id) return 1; + /* Test if there is any vendor ID. */ + if (GENERIC_MANUF_ID == flash->manufacture_id && + id1 != 0xff) + return 1; + return 0; } @@ -329,6 +334,11 @@ GENERIC_DEVICE_ID == flash->model_id) return 1; + /* Test if there is any vendor ID. */ + if (GENERIC_MANUF_ID == flash->manufacture_id && + id1 != 0xff) + return 1; + return 0; } -- http://www.hailfinger.org/

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Fix feature detection when fdti requires libusb for linking
by Joerg Mayer Nov. 16, 2009

Nov. 16, 2009

see attached patch. patch is too small to be copyrightable... ciao Joerg -- Joerg Mayer <jmayer(a)loplof.de> We are stuck with technology when what we really want is just stuff that works. Some say that should read Microsoft instead of technology.

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Board enable for EPoX EP-8RDA3+ lspci fix
by . . Oct. 5, 2009

Oct. 5, 2009

Hi, seems hotmail leaves out parts of the lspci output, so pastebinned it here: http://coreboot.pastebin.com/f22a57659 Link should stay 'forever'. Thanks, Anol. _________________________________________________________________ With Windows Live, you can organize, edit, and share your photos. http://www.microsoft.com/middleeast/windows/windowslive/products/photo-gall…

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"ERASED FAILED!" messages for ICH2 / SST49LF0002A/B
by Allan Bjorklund Oct. 5, 2009

Oct. 5, 2009

Hello, I'm wanting to upgrade the BIOS on an older machine that I have. A Sony Vaio (PCV-RX650(UC)), with an ASUSTeK mother board (P4B266LM Rev: 1.xx), running Linux kernel 2.6.28. Running flashrom (today's trunk version) with no arguments gives this: flashrom v0.9.1-runknown No coreboot table found. Found chipset "Intel ICH2", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF002A/B" (256 KB, FWH) at physical address 0xfffc0000. No operations were specified. I saved a copy of my existing BIOS image with: flashrom -r original_bios.bin That appears to work, as the file is the same size as the updated BIOS .bin file I downloaded from the vendor's site. To test writing, I attempted to write the original BIOS image back with flashrom -w original_bios.bin, and here is the output: flashrom v0.9.1-runknown No coreboot table found. Found chipset "Intel ICH2", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF002A/B" (256 KB, FWH) at physical address 0xfffc0000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x25, failed byte count from 0x00000000-0x00003fff: 0x3fa4 ERASE FAILED! ERASE FAILED! ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! If I do a flashrom -v original_bios.bin, I get: flashrom v0.9.1-runknown No coreboot table found. Found chipset "Intel ICH2", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF002A/B" (256 KB, FWH) at physical address 0xfffc0000. Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED. And reading a second copy and doing a binary diff shows no differences, so my BIOS checks out as not being damaged. (At least, I think so.) So, any advice on what to look for/change to make this work? Thanks. --Allan

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