Hi,
I'm trying to find out which external programmers should be supported next.
1. There was talk of an AVR-based new programmer using the serprog
protocol on IRC by someone with the nick "coldelectrons", but I have no
idea if he/she is reading this mail. IMHO more hardware using the
serprog protocol is always a good idea.
2. All those Willem/Sivava variants. People regularly request those, but
I don't think anyone in here owns the hardware.
3. RayeR's SPIPGM. I have a preliminary patch which could work, but I
don't have the hardware. Will send the patch to the list soon.
4. LPC^2, Milksop, CheapLPC and other programmers from the Xbox modding
community.
5. Dozens of SPI programmer hardware projects scattered over the net.
Too many to count, and I'm not sure which of them has more than one user.
In general, it seems creating a new programmer hardware design is like
writing IRC clients: A nice way to get started in the field. I have no
problems merging flashrom support for all of them, but I won't implement
support for all of them myself.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
Hi Vadim,
thanks for your mail. I have added the flashrom mailing list in CC:
because we should develop a generic way to handle DualBIOS and similar
techniques.
On 09.04.2010 08:12, Vadim Girlin wrote:
> I'm going to try coreboot on Gigabyte GA-MA770-UD3.
> It's AMD 770 (RX780 / SB700).
>
> My motherboard supports hardware dual bios - with two chips on it.
> I'm going to try flashing backup chip and boot from it. It seems to be
> possible - I've tested it (flashing at least). Chips on this board could
> be switched by changing bit 0 at undocumented register EF on LDN 7 of
> IT8720. I can use slightly patched flashrom for accessing any chip I
> want without any problems. And this is tested many times.
>
> My idea is to use backup chip for debugging - that always keeps my
> chance to reboot from main bios chip. And removes the need for
> desoldering etc.
>
> And second problem is that original bios is checking second chip - and
> trying to recover it by flashing the bios from main chip on reboot?
> rewriting coreboot. AFAICS this could be solved by including some
> signatures etc. It seems to be easy to find out. May be someone is
> working on this?
>
> BTW I can send the patch for flashrom - but I think that with
> information I mentioned above somebody could make it much better than my
> ugly hack. I hope the regs should be the same for all latest Gigabyte
> MBs using IT8720/18
>
It would be great if you could send that patch. It will help us make a
flashrom design decision that works for all boards with multiple flash
chips.
By the way, some of us have good contacts at ITE, so we can ask ITE for
details about the undocumented registers.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
Hello folks,
I would like to use a flashrom utility to access 2 serial flashes on
the SPI bus of my x86 board, but I'm struggling with the second one.
So I'm looking for any help, hints or advices which can help me to
solve this issue.
I have custom x86 board (Atom n450 CPU, ICH8M chipset) which have 2
serial flashes installed on it.
The first one is SST25VF016B and the second one is Numonyx M45PE16.
The M45PE16 is pretty the similar to the M25PE16.
Both this chips are connected to the SPI bus of the ICH8M chipset, the
CS (chip select) signal of the SST25VF is routed to the SPI_CS0 and
the CS signal of the M45PE16 is routed to the SPI_CS1.
I can successfully read, erase and write the SST flash.
Trying to figure out if flashrom utility can find the second Numonyx
flash I've added the proper description for it to the flashchips.c
(actually I've leaved it the same as for M25PE16 but changed model_id
field). Unfortunately it didn't help me at all.
So I'm wondering if flashrom can't find M45PE16 flash because of
cleared SPI_CS1 signal and how can I enable it?
Does flashrom utility support such kind of configurations or does it
simply searching for the flash on CS0?
Probably some of you have some ideas on enabling SPI_CS1 or even some
useful links etc.
Unfortunately the official Intel ICH8M documentation looks kind of
complicated and no so clear to me.
I'll of course digg into it but any help, hints or advices are highly
appreciated!
Thanks in advance,
xborodax.
Hi Mike,
On 23.02.2010 05:45, Spangler, Mike T wrote:
> I can probe with a continuity tester, but would need to know specific
> pin locations to try. Do you have any generic info on doing this?
Yes (well, I'd have to write up something), but the solution mentioned
by Michael is way easier, so I'll wait until Michael has diagnosed the
GPIO settings from the flashrom run on factory BIOS.
Regards,
Carl-Daniel
--
"I do consider assignment statements and pointer variables to be among
computer science's most valuable treasures."
-- Donald E. Knuth
On Fri, 12 Mar 2010, Michael Karcher wrote:
> Was introduced in r926. Found by Henrik Kretzschmar <henne(a)nachtwindheim.de>.
>
> Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de>
Imo looks sane and should be commited.
Acked-by: Maciej Pijanka <maciej.pijanka(a)gmail.com>
> ---
> board_enable.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/board_enable.c b/board_enable.c
> index aa463bc..0e89137 100644
> --- a/board_enable.c
> +++ b/board_enable.c
> @@ -1445,7 +1445,7 @@ int board_flash_enable(const char *vendor, const char *part)
> if (!board)
> board = board_match_pci_card_ids();
>
> - if (board->status == NT) {
> + if (board && board->status == NT) {
> if (!force_boardenable)
> {
> printf("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
> --
--
Maciej Pijanka
I don't fear computers, I fear lack of them -- Isaac Asimov
Currently messages like "Writing flash chip..." that don't end with a
newline are buffered until the operation is complete, unless the
particular write function generates status output in the meantime.
Flushing stdout after each message ensures that the message appears
immediately.
Signed-off-by: Ed Swierk <eswierk(a)aristanetworks.com>
---
Index: flashrom-0.9.2-r1057/cli_output.c
===================================================================
--- flashrom-0.9.2-r1057.orig/cli_output.c
+++ flashrom-0.9.2-r1057/cli_output.c
@@ -47,5 +47,6 @@ int print(int type, const char *fmt, ...
va_start(ap, fmt);
ret = vfprintf(output_type, fmt, ap);
va_end(ap);
+ fflush(output_type);
return ret;
}
On 5/14/10 3:06 PM, Michael Karcher wrote:
> Am Freitag, den 14.05.2010, 14:48 +0200 schrieb Stefan Reinauer:
>
>> On 4/16/10 6:21 PM, Stefan Reinauer wrote:
>>
>>> Look at the return value of wait_82802ab()
>>> Index: sst49lfxxxc.c
>>> ===================================================================
>>> --- sst49lfxxxc.c (revision 993)
>>> +++ sst49lfxxxc.c (working copy)
>>> @@ -84,6 +84,7 @@
>>> chip_writeb(0xD0, bios + address);
>>>
>>> status = wait_82802ab(bios);
>>> + print_status_82802ab(status);
>>>
> [...]
> basically a good idea, but printing one status dump per erased block
> seems a bit excessive, even in verbose mode, as there are some chips
> with 4K sector size. Could you limit status printing to "status !=
> 0x80", as this is "ready, no error bits"?
>
That's what the 82802ab and sharp lhf00l04 do, too. So if you think the
behavior should be changed, you should change it in all three places.
Stefan
