Hi,
we're hitting the 80 column limit in our code in ways which actually
reduce readability for the code. Examples are various multiline messages
and complicated nested code where refactoring to a separate function
doesn't make sense.
Keeping the old 80 column limit is not really an option anymore.
Standard terminal sizes have one of 80, 100 or 132 columns.
Given the monitor resolutions many people have nowadays, I think it is
safe to say that you can fit two xterms with 100 columns horizonally
next to each other. 100 columns should also be sufficient for a msg_p*
of roughly 80 columns of text.
132 columns provide more leeway, but IMHO that would be too wide for
good readability (and my screen can't fit two xterms side-by-side anymore).
Of course some files have sections where any column limit is not
acceptable (board lists etc.), but the column limit violations should be
limited to the affected file sections, not whole files.
Comments?
I'd like to get this decided today or tomorrow so we know where we need
line breaks in Stefan Tauner's new struct flashchip patch.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
I have a spansion S25FL128P......X chip and can do some tests.
The "problem" is that i don't know if its an 0 or an 1.
On the chip i see only "FL128PIF" and one line lower i see "00299012 C".
Probing works (id1 0x01, id2 0x2018):
Calibrating delay loop... OK.
serprog: Programmer name is "serprog-duino"
Found Spansion flash chip "S25FL128P......0" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL128P......1" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL128S......0" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL128S......1" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL129P......0" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL129P......1" (16384 kB, SPI) on serprog.
Multiple flash chip definitions match the detected chip(s):
"S25FL128P......0", "S25FL128P......1", "S25FL128S......0",
"S25FL128S......1", "S25FL129P......0", "S25FL129P......1"
Please specify which chip definition to use with the -c <chipname> option.
BTW: Chip was fund on a Dell-Systemboard.
Hi,
I'm trying to find out which external programmers should be supported next.
1. There was talk of an AVR-based new programmer using the serprog
protocol on IRC by someone with the nick "coldelectrons", but I have no
idea if he/she is reading this mail. IMHO more hardware using the
serprog protocol is always a good idea.
2. All those Willem/Sivava variants. People regularly request those, but
I don't think anyone in here owns the hardware.
3. RayeR's SPIPGM. I have a preliminary patch which could work, but I
don't have the hardware. Will send the patch to the list soon.
4. LPC^2, Milksop, CheapLPC and other programmers from the Xbox modding
community.
5. Dozens of SPI programmer hardware projects scattered over the net.
Too many to count, and I'm not sure which of them has more than one user.
In general, it seems creating a new programmer hardware design is like
writing IRC clients: A nice way to get started in the field. I have no
problems merging flashrom support for all of them, but I won't implement
support for all of them myself.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
Good morning,
I am trying to revive a computer which had a failed BIOS update.
I bought a BUS Pirate and started using Flashrom to take a copy of an identical fully working model. Strangely this machine has two chips:
MX25L6405D
MX25L3205D
>From the dump's I have made, I believe the MX25L6405D holds the BIOS and the MX25L3205D possibly holds the ME Firmware.
Don't know if this is any use but an output from fptw64 on the working machine shows me the following:
C:\FPTw64>fptw64.exe -i
Intel (R) Flash Programming Tool. Version: 8.0.10.1464
Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.
Platform: Intel(R) Q77 Express Chipset
Reading HSFSTS register... Flash Descriptor: Valid
--- Flash Devices Found ---
MX25L6405D ID:0xC22017 Size: 8192KB (65536Kb)
MX25L3205D ID:0xC22016 Size: 4096KB (32768Kb)
--- Flash Image Information --
Signature: VALID
Number of Flash Components: 2
Component 1 - 8192KB (65536Kb)
Component 2 - 4096KB (32768Kb)
Regions:
Descriptor - Base: 0x000000, Limit: 0x000FFF
BIOS - Base: 0x600000, Limit: 0xBFFFFF
ME - Base: 0x005000, Limit: 0x5FFFFF
GbE - Base: 0x001000, Limit: 0x004FFF
PDR - Not present
Master Region Access:
CPU/BIOS - ID: 0x0000, Read: 0x0B, Write: 0x0A
ME - ID: 0x0000, Read: 0x0D, Write: 0x0C
GbE - ID: 0x0118, Read: 0x08, Write: 0x08
Total Accessable SPI Memory: 12288KB, Total Installed SPI Memory : 12288KB
I am struggling to properly erase/write to both of these chips so I wondered if you could offer any advise on trying to get this working?
These are the errors I am getting on both chips, have tried with both Linux and Windows on each chip and get pretty much the same output:
flashrom v0.9.7-r1711 on Linux 3.14.48-std454-amd64 (x86_64)
flashrom was built with libpci 3.2.0, GCC 4.8.4, little endian
Command line (8 args): flashrom -p buspirate_spi:dev=/dev/ttyUSB0, -c MX25L6405(D) -E -V -o /media/usb/log2.txt
Calibrating delay loop... OS timer resolution is 1 usecs, 1456M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 997 us, 10000 myus = 9996 us, 4 myus = 4 us, OK.
Initializing buspirate_spi programmer
Baud rate is 115200.
Detected Bus Pirate hardware v3.a
Detected Bus Pirate firmware 6.3 ("v6.3-beta1")
Using SPI command set v2.
SPI speed is 8MHz
Raw bitbang mode version 1
Raw SPI mode version 1
The following protocols are supported: SPI.
Probing for Macronix MX25L6405(D), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017
Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on buspirate_spi.
Chip status register is 0x80.
Chip status register: Status Register Write Disable (SRWD, SRP, ...) is set
Chip status register: Bit 6 is not set
Chip status register: Block Protect 3 (BP3) is not set
Chip status register: Block Protect 2 (BP2) is not set
Chip status register: Block Protect 1 (BP1) is not set
Chip status register: Block Protect 0 (BP0) is not set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
This chip may contain one-time programmable memory. flashrom cannot read
and may never be able to write it, hence it may not be able to completely
clone the contents of this chip (see man page for details).
Block protection is disabled.
Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:EFAILED at 0x00001000! Expected=0xff, Found=0x90, failed byte count from 0x00000000-0x0000ffff: 0x3aa8
ERASE FAILED!
Reading current flash chip contents...
At one point the above was the same output as below that everything was set but still failed on "unsetting lock bits" but I have forgotten to save that output.
flashrom was built with GCC 4.9.2, little endian
Command line (6 args): flashrom -p buspirate_spi:dev=COM3 -c MX25L3205D/MX25L3208D -E -V
Calibrating delay loop... OS timer resolution is 501 usecs, 1771M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 1000 us, 10000 myus = 10008 us, 2004 myus = 2002 us, OK.
Initializing buspirate_spi programmer
Baud rate is 115200.
Detected Bus Pirate hardware v3.a
Detected Bus Pirate firmware 6.3
Using SPI command set v2.
SPI speed is 8MHz
Raw bitbang mode version 1
Raw SPI mode version 1
The following protocols are supported: SPI.
Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016
Found Macronix flash chip "MX25L3205D/MX25L3208D" (4096 kB, SPI) on buspirate_spi.
Chip status register is 0xff.
Chip status register: Status Register Write Disable (SRWD, SRP, ...) is set
Chip status register: Bit 6 is set
Chip status register: Block Protect 3 (BP3) is set
Chip status register: Block Protect 2 (BP2) is set
Chip status register: Block Protect 1 (BP1) is set
Chip status register: Block Protect 0 (BP0) is set
Chip status register: Write Enable Latch (WEL) is set
Chip status register: Write In Progress (WIP/BUSY) is set
This chip may contain one-time programmable memory. flashrom cannot read
and may never be able to write it, hence it may not be able to completely
clone the contents of this chip (see man page for details).
Some block protection in effect, disabling...
Need to disable the register lock first... Unsetting lock bit(s) failed.
Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:EFAILED at 0x00000000! Expected=0xff, Found=0xe8, failed byte count from 0x00000000-0x00000fff: 0x1000
ERASE FAILED!
Reading current flash chip contents... ^C
This is a link to the datasheet for both chips : http://www.macronix.com/Lists/DataSheet/Attachments/2453/MX25L6405D,%203V,%…
It mentions something about having to give 9.5v-10.5v to the WP pin so maybe that is the problem? does this mean i would have to externally source this voltage outside of bus pirate to enable write enable properly?
Many Thanks
Hi,
I have a Dell OptiPlex 755 USFF which has an Atmel AT26DF321 SPI flash
chip (which is like an AT25DF321 and has the same device ID except it
doesn't have a HOLD# pin). I've used flashrom to read and write the
same chip on another board by ISP using a BeagleBone Black, 10-cm jumper
cables, a SOIC clip, and an ATX PSU.
However, flashrom with the same ISP setup fails to probe the chip on the
OptiPlex. I've tried two different known-working BBBs, different
cables, two different Pomona SOIC clips, connecting WP# to 3.3 V,
connecting what would be HOLD# on the AT25 to 3.3 V, and different
spispeed clock frequencies from 1 kHz to 10 MHz.
I've tried powering the chip (and the rest of the board's 3.3-V rail)
with a 3.3-V line of the ATX PSU, and I've tried instead powering the
whole board with the computer's 12-V PSU. I've also tried running
flashrom while holding down the power button to keep the system in
reset. Following some advice on <http://flashrom.org/ISP> I even tried
removing the DIMMs and CPU.
Every time I get only bytes of 0xff from the chip, as in the attached
log. In my experience that usually means either the programmer isn't
properly connected to the chip or the programmer uses a different data
voltage than the chip does. But I've checked and rechecked all of the
connections, and I know both the BBB and the AT26DF321 use 3.3-V data
signals.
Unfortunately there don't seem to be any schematics available for this
board (Dell model number 0HX555, ODM model number HX533 A00, ODM might
be Asustek or MiTAC). This system does have an Intel Management Engine
in the northbridge, but even if that was running I should at least be
able to probe the chip and read its contents.
Does anyone have any ideas of anything else I could try (short of
desoldering the chip from the board) or about what the problem may be?
Thanks,
--
Patrick "P. J." McDermott
http://www.pehjota.net/
Lead Developer, ProteanOS
http://www.proteanos.com/
Apart from the JEDEC ID (621614) the difference from the SST25WF080 is that
it lacks op codes 0xAD (AAI Word program) and 0x52 (32K erase).
Tested under Linux with spidev.
Signed-off-by: Ben Gardner <bgardner(a)wabtec.com>
---
flashchips.c | 35 +++++++++++++++++++++++++++++++++++
flashchips.h | 3 ++-
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/flashchips.c b/flashchips.c
index 8b5d1ec..b71bd2c 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -11803,6 +11803,41 @@ const struct flashchip flashchips[] = {
{
.vendor = "SST",
+ .name = "SST25WF080B",
+ .bustype = BUS_SPI,
+ .manufacture_id = SST_ID_62,
+ .model_id = SST_SST25WF080B,
+ .total_size = 1024,
+ .page_size = 256,
+ .feature_bits = FEATURE_WRSR_EITHER,
+ .tested = TEST_OK_PREW,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 256} },
+ .block_erase = spi_block_erase_20,
+ }, {
+ .eraseblocks = { {64 * 1024, 16} },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {1024 * 1024, 1} },
+ .block_erase = spi_block_erase_60,
+ }, {
+ .eraseblocks = { {1024 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ },
+ },
+ .printlock = spi_prettyprint_status_register_sst25, /* *does* have a BP3 but it is useless */
+ .unlock = spi_disable_blockprotect_bp3_srwd,
+ .write = spi_chip_write_256,
+ .read = spi_chip_read, /* Fast read (0x0B) supported */
+ .voltage = {1650, 1950},
+ },
+
+ {
+ .vendor = "SST",
.name = "SST28SF040A",
.bustype = BUS_PARALLEL,
.manufacture_id = SST_ID,
diff --git a/flashchips.h b/flashchips.h
index 07ae49d..d6b2b8d 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -659,6 +659,7 @@
* byte of device ID is related to log(bitsize) at least for some chips.
*/
#define SST_ID 0xBF /* SST */
+#define SST_ID_62 0x62 /* SST */
#define SST_SST25LF020_REMS 0x43 /* REMS or RES opcode */
#define SST_SST25WF512 0x2501
#define SST_SST25WF010 0x2502
@@ -669,7 +670,7 @@
* IDs and were not spotted in the wild yet. Their datasheets show a 4 byte long response w/o a vendor ID. */
#define SST_SST25WF020A /* 0x62 0x16 0x12 0x00 */
#define SST_SST25WF040B /* 0x62 0x16 0x13 0x00 */
-#define SST_SST25WF080B /* 0x62 0x16 0x14 0x00 */
+#define SST_SST25WF080B 0x1614 /* 0x62 0x16 0x14 0x00 */
#define SST_SST25VF512_REMS 0x48 /* REMS or RES opcode, same as SST25VF512A */
#define SST_SST25VF010_REMS 0x49 /* REMS or RES opcode, same as SST25VF010A */
#define SST_SST25VF020_REMS 0x43 /* REMS or RES opcode, same as SST25LF020A */
--
1.9.1
This email and any attachments are only for use by the intended recipient(s) and may contain legally privileged, confidential, proprietary or otherwise private information. Any unauthorized use, reproduction, dissemination, distribution or other disclosure of the contents of this e-mail or its attachments is strictly prohibited. If you have received this email in error, please notify the sender immediately and delete the original. Neither this information block, the typed name of the sender, nor anything else in this message is intended to constitute an electronic signature unless a specific statement to the contrary is included in this message.