Hi,
we're hitting the 80 column limit in our code in ways which actually
reduce readability for the code. Examples are various multiline messages
and complicated nested code where refactoring to a separate function
doesn't make sense.
Keeping the old 80 column limit is not really an option anymore.
Standard terminal sizes have one of 80, 100 or 132 columns.
Given the monitor resolutions many people have nowadays, I think it is
safe to say that you can fit two xterms with 100 columns horizonally
next to each other. 100 columns should also be sufficient for a msg_p*
of roughly 80 columns of text.
132 columns provide more leeway, but IMHO that would be too wide for
good readability (and my screen can't fit two xterms side-by-side anymore).
Of course some files have sections where any column limit is not
acceptable (board lists etc.), but the column limit violations should be
limited to the affected file sections, not whole files.
Comments?
I'd like to get this decided today or tomorrow so we know where we need
line breaks in Stefan Tauner's new struct flashchip patch.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
I have a spansion S25FL128P......X chip and can do some tests.
The "problem" is that i don't know if its an 0 or an 1.
On the chip i see only "FL128PIF" and one line lower i see "00299012 C".
Probing works (id1 0x01, id2 0x2018):
Calibrating delay loop... OK.
serprog: Programmer name is "serprog-duino"
Found Spansion flash chip "S25FL128P......0" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL128P......1" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL128S......0" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL128S......1" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL129P......0" (16384 kB, SPI) on serprog.
Found Spansion flash chip "S25FL129P......1" (16384 kB, SPI) on serprog.
Multiple flash chip definitions match the detected chip(s):
"S25FL128P......0", "S25FL128P......1", "S25FL128S......0",
"S25FL128S......1", "S25FL129P......0", "S25FL129P......1"
Please specify which chip definition to use with the -c <chipname> option.
BTW: Chip was fund on a Dell-Systemboard.
Hi,
we obviously want to participate in FOSDEM.
https://fosdem.org/2016/news/2015-09-24-call-for-participation/
ACT NOW!
Some deadlines already expired. Some can still be managed.
Main track talks: Deadline 2015-10-30 (10 days left)
One hour of entertainment, huge audience.
Anyone up for the challenge?
Stands: Deadline 2015-11-13 (24 days left)
I can send in the proposal if I'm not going to be alone there.
How many tables do we want for our stand/booth(s)?
Who is coming?
Lightning talks: Deadline 2015-11-27 (38 days left)
Short and to the point. Your 15-minute elevator pitch.
Can you sell the project?
All deadlines are at 23.59 UTC
Developer room proposal: Deadline EXPIRED
Maybe some developer room will accept talks/demos from us.
Regards,
Carl-Daniel
Today I was about to try write support for flashrom with the Xi 3650
BIOS and see whether it would work. The two images used for write were
not too different (the only difference was a BIOS setting letting you
choose between the on-board graphics card and an Nvidia Geforce 9600M
GT). Nonetheless it seems to have written (and erased) at least one
block of the BIOS ROM correctly.
Yours,
Elmar
P.S. the console screenshot:
Proceeding anyway because user forced us to.
Found chipset "Intel ICH9M-E". Enabling flash write... OK.
Found Winbond flash chip "W25X16" (2048 kB, SPI) at physical address
0xffe00000.
Reading flash... done.
root@sysresccd /usb/Xi3650-BIOS/flashrom-T6400 % ls
intermediate Xi3650-T6400-1.0B-1646-0020.rom
Xi3650-T6400-1.0H-1646-0024-IGD-2ndflash.rom
root@sysresccd /usb/Xi3650-BIOS/flashrom-T6400 % cmp
Xi3650-T6400-1.0H-1646-0024-IGD-2ndflash.rom
intermediate/Xi3650-T6400-1.0H-1646-0024-IGD.rom
Xi3650-T6400-1.0H-1646-0024-IGD-2ndflash.rom
intermediate/Xi3650-T6400-1.0H-1646-0024-IGD.rom differ: char 1575900,
line 3706
root@sysresccd /usb/Xi3650-BIOS/flashrom-T6400 % ls
intermediate Xi3650-T6400-1.0B-1646-0020.rom
Xi3650-T6400-1.0H-1646-0024-IGD-2ndflash.rom
root@sysresccd /usb/Xi3650-BIOS/flashrom-T6400 % flashrom -p
internal:laptop=force_I_want_a_brick --write
intermediate/Xi3650-T6400-1.0H-1646-0024-Nvidia.rom
flashrom v0.9.7-r1711 on Linux 3.14.50-std460-amd64 (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
========================================================================
WARNING! You seem to be running flashrom on an unsupported laptop.
Laptops, notebooks and netbooks are difficult to support and we
recommend to use the vendor flashing utility. The embedded controller
(EC) in these machines often interacts badly with flashing.
See the manpage and http://www.flashrom.org/Laptops for details.
If flash is shared with the EC, erase is guaranteed to brick your laptop
and write may brick your laptop.
Read and probe may irritate your EC and cause fan failure, backlight
failure and sudden poweroff.
You have been warned.
========================================================================
Proceeding anyway because user forced us to.
Found chipset "Intel ICH9M-E". Enabling flash write... OK.
Found Winbond flash chip "W25X16" (2048 kB, SPI) at physical address
0xffe00000.
Reading old flash chip contents... done.
Erasing and writing flash chip... Erase/write done.
Verifying flash... VERIFIED.
root@sysresccd /usb/Xi3650-BIOS/flashrom-T6400 % flashrom -p
internal:laptop=force_I_want_a_brick --write
Xi3650-T6400-1.0H-1646-0024-IGD-2ndflash.rom
flashrom v0.9.7-r1711 on Linux 3.14.50-std460-amd64 (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
========================================================================
WARNING! You seem to be running flashrom on an unsupported laptop.
Laptops, notebooks and netbooks are difficult to support and we
recommend to use the vendor flashing utility. The embedded controller
(EC) in these machines often interacts badly with flashing.
See the manpage and http://www.flashrom.org/Laptops for details.
If flash is shared with the EC, erase is guaranteed to brick your laptop
and write may brick your laptop.
Read and probe may irritate your EC and cause fan failure, backlight
failure and sudden poweroff.
You have been warned.
========================================================================
Proceeding anyway because user forced us to.
Found chipset "Intel ICH9M-E". Enabling flash write... OK.
Found Winbond flash chip "W25X16" (2048 kB, SPI) at physical address
0xffe00000.
Reading old flash chip contents... done.
Erasing and writing flash chip... Erase/write done.
Verifying flash... VERIFIED.
root@sysresccd /usb/Xi3650-BIOS/flashrom-T6400 %
Hi,
I'm trying to find out which external programmers should be supported next.
1. There was talk of an AVR-based new programmer using the serprog
protocol on IRC by someone with the nick "coldelectrons", but I have no
idea if he/she is reading this mail. IMHO more hardware using the
serprog protocol is always a good idea.
2. All those Willem/Sivava variants. People regularly request those, but
I don't think anyone in here owns the hardware.
3. RayeR's SPIPGM. I have a preliminary patch which could work, but I
don't have the hardware. Will send the patch to the list soon.
4. LPC^2, Milksop, CheapLPC and other programmers from the Xbox modding
community.
5. Dozens of SPI programmer hardware projects scattered over the net.
Too many to count, and I'm not sure which of them has more than one user.
In general, it seems creating a new programmer hardware design is like
writing IRC clients: A nice way to get started in the field. I have no
problems merging flashrom support for all of them, but I won't implement
support for all of them myself.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
Good morning,
I am trying to revive a computer which had a failed BIOS update.
I bought a BUS Pirate and started using Flashrom to take a copy of an identical fully working model. Strangely this machine has two chips:
MX25L6405D
MX25L3205D
>From the dump's I have made, I believe the MX25L6405D holds the BIOS and the MX25L3205D possibly holds the ME Firmware.
Don't know if this is any use but an output from fptw64 on the working machine shows me the following:
C:\FPTw64>fptw64.exe -i
Intel (R) Flash Programming Tool. Version: 8.0.10.1464
Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.
Platform: Intel(R) Q77 Express Chipset
Reading HSFSTS register... Flash Descriptor: Valid
--- Flash Devices Found ---
MX25L6405D ID:0xC22017 Size: 8192KB (65536Kb)
MX25L3205D ID:0xC22016 Size: 4096KB (32768Kb)
--- Flash Image Information --
Signature: VALID
Number of Flash Components: 2
Component 1 - 8192KB (65536Kb)
Component 2 - 4096KB (32768Kb)
Regions:
Descriptor - Base: 0x000000, Limit: 0x000FFF
BIOS - Base: 0x600000, Limit: 0xBFFFFF
ME - Base: 0x005000, Limit: 0x5FFFFF
GbE - Base: 0x001000, Limit: 0x004FFF
PDR - Not present
Master Region Access:
CPU/BIOS - ID: 0x0000, Read: 0x0B, Write: 0x0A
ME - ID: 0x0000, Read: 0x0D, Write: 0x0C
GbE - ID: 0x0118, Read: 0x08, Write: 0x08
Total Accessable SPI Memory: 12288KB, Total Installed SPI Memory : 12288KB
I am struggling to properly erase/write to both of these chips so I wondered if you could offer any advise on trying to get this working?
These are the errors I am getting on both chips, have tried with both Linux and Windows on each chip and get pretty much the same output:
flashrom v0.9.7-r1711 on Linux 3.14.48-std454-amd64 (x86_64)
flashrom was built with libpci 3.2.0, GCC 4.8.4, little endian
Command line (8 args): flashrom -p buspirate_spi:dev=/dev/ttyUSB0, -c MX25L6405(D) -E -V -o /media/usb/log2.txt
Calibrating delay loop... OS timer resolution is 1 usecs, 1456M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 997 us, 10000 myus = 9996 us, 4 myus = 4 us, OK.
Initializing buspirate_spi programmer
Baud rate is 115200.
Detected Bus Pirate hardware v3.a
Detected Bus Pirate firmware 6.3 ("v6.3-beta1")
Using SPI command set v2.
SPI speed is 8MHz
Raw bitbang mode version 1
Raw SPI mode version 1
The following protocols are supported: SPI.
Probing for Macronix MX25L6405(D), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017
Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on buspirate_spi.
Chip status register is 0x80.
Chip status register: Status Register Write Disable (SRWD, SRP, ...) is set
Chip status register: Bit 6 is not set
Chip status register: Block Protect 3 (BP3) is not set
Chip status register: Block Protect 2 (BP2) is not set
Chip status register: Block Protect 1 (BP1) is not set
Chip status register: Block Protect 0 (BP0) is not set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
This chip may contain one-time programmable memory. flashrom cannot read
and may never be able to write it, hence it may not be able to completely
clone the contents of this chip (see man page for details).
Block protection is disabled.
Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:EFAILED at 0x00001000! Expected=0xff, Found=0x90, failed byte count from 0x00000000-0x0000ffff: 0x3aa8
ERASE FAILED!
Reading current flash chip contents...
At one point the above was the same output as below that everything was set but still failed on "unsetting lock bits" but I have forgotten to save that output.
flashrom was built with GCC 4.9.2, little endian
Command line (6 args): flashrom -p buspirate_spi:dev=COM3 -c MX25L3205D/MX25L3208D -E -V
Calibrating delay loop... OS timer resolution is 501 usecs, 1771M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 1000 us, 10000 myus = 10008 us, 2004 myus = 2002 us, OK.
Initializing buspirate_spi programmer
Baud rate is 115200.
Detected Bus Pirate hardware v3.a
Detected Bus Pirate firmware 6.3
Using SPI command set v2.
SPI speed is 8MHz
Raw bitbang mode version 1
Raw SPI mode version 1
The following protocols are supported: SPI.
Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016
Found Macronix flash chip "MX25L3205D/MX25L3208D" (4096 kB, SPI) on buspirate_spi.
Chip status register is 0xff.
Chip status register: Status Register Write Disable (SRWD, SRP, ...) is set
Chip status register: Bit 6 is set
Chip status register: Block Protect 3 (BP3) is set
Chip status register: Block Protect 2 (BP2) is set
Chip status register: Block Protect 1 (BP1) is set
Chip status register: Block Protect 0 (BP0) is set
Chip status register: Write Enable Latch (WEL) is set
Chip status register: Write In Progress (WIP/BUSY) is set
This chip may contain one-time programmable memory. flashrom cannot read
and may never be able to write it, hence it may not be able to completely
clone the contents of this chip (see man page for details).
Some block protection in effect, disabling...
Need to disable the register lock first... Unsetting lock bit(s) failed.
Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:EFAILED at 0x00000000! Expected=0xff, Found=0xe8, failed byte count from 0x00000000-0x00000fff: 0x1000
ERASE FAILED!
Reading current flash chip contents... ^C
This is a link to the datasheet for both chips : http://www.macronix.com/Lists/DataSheet/Attachments/2453/MX25L6405D,%203V,%…
It mentions something about having to give 9.5v-10.5v to the WP pin so maybe that is the problem? does this mean i would have to externally source this voltage outside of bus pirate to enable write enable properly?
Many Thanks