flashrom November 2015

flashrom@flashrom.org

27 participants
78 discussions

[PATCH] Add support for SST25WF080B 1 MB flash.
by Ben Gardner 22 Nov '15

22 Nov '15

Apart from the JEDEC ID (621614) the difference from the SST25WF080 is that it lacks op codes 0xAD (AAI Word program) and 0x52 (32K erase). Tested under Linux with spidev. Signed-off-by: Ben Gardner <bgardner(a)wabtec.com> --- flashchips.c | 35 +++++++++++++++++++++++++++++++++++ flashchips.h | 3 ++- 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/flashchips.c b/flashchips.c index 8b5d1ec..b71bd2c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -11803,6 +11803,41 @@ const struct flashchip flashchips[] = { { .vendor = "SST", + .name = "SST25WF080B", + .bustype = BUS_SPI, + .manufacture_id = SST_ID_62, + .model_id = SST_SST25WF080B, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_EITHER, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_sst25, /* *does* have a BP3 but it is useless */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {1650, 1950}, + }, + + { + .vendor = "SST", .name = "SST28SF040A", .bustype = BUS_PARALLEL, .manufacture_id = SST_ID, diff --git a/flashchips.h b/flashchips.h index 07ae49d..d6b2b8d 100644 --- a/flashchips.h +++ b/flashchips.h @@ -659,6 +659,7 @@ * byte of device ID is related to log(bitsize) at least for some chips. */ #define SST_ID 0xBF /* SST */ +#define SST_ID_62 0x62 /* SST */ #define SST_SST25LF020_REMS 0x43 /* REMS or RES opcode */ #define SST_SST25WF512 0x2501 #define SST_SST25WF010 0x2502 @@ -669,7 +670,7 @@ * IDs and were not spotted in the wild yet. Their datasheets show a 4 byte long response w/o a vendor ID. */ #define SST_SST25WF020A /* 0x62 0x16 0x12 0x00 */ #define SST_SST25WF040B /* 0x62 0x16 0x13 0x00 */ -#define SST_SST25WF080B /* 0x62 0x16 0x14 0x00 */ +#define SST_SST25WF080B 0x1614 /* 0x62 0x16 0x14 0x00 */ #define SST_SST25VF512_REMS 0x48 /* REMS or RES opcode, same as SST25VF512A */ #define SST_SST25VF010_REMS 0x49 /* REMS or RES opcode, same as SST25VF010A */ #define SST_SST25VF020_REMS 0x43 /* REMS or RES opcode, same as SST25LF020A */ -- 1.9.1 This email and any attachments are only for use by the intended recipient(s) and may contain legally privileged, confidential, proprietary or otherwise private information. Any unauthorized use, reproduction, dissemination, distribution or other disclosure of the contents of this e-mail or its attachments is strictly prohibited. If you have received this email in error, please notify the sender immediately and delete the original. Neither this information block, the typed name of the sender, nor anything else in this message is intended to constitute an electronic signature unless a specific statement to the contrary is included in this message.

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Re: [flashrom] flashrom on PowerPC
by Stefan Tauner 22 Nov '15

22 Nov '15

On Fri, 20 Nov 2015 17:16:44 +0100 Peter Lemenkov <lemenkov(a)gmail.com> wrote: > Hello All! > > 2011-10-23 0:20 GMT+02:00 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: > > On Wed, 27 Jul 2011 18:20:19 +0200 > > Mattias Mattsson <vitplister(a)gmail.com> wrote: > > > >> Hi all, > >> > >> I was able to run flashrom under Linux on PPC (big endian) hardware > >> with two small modifications in internal.c and processor_enable.c (see > >> attached patch). Not sure if this is the right way to do it but it > >> seems to work for me. > >> > > > > i am resending this patch (unchanged) because patchwork did not pick it > > up correctly. please do send one patch per mail only in the future > > until we have something really working. :) > > Sorry for bringing up this again but what's the status of this? It > does works on old PPC-based Apple Macs and it still applies cleanly. > Maybe it's time to apply this, otherwise we won't see any potential > users very soon :) Hi Peter, it does not apply to the current version, but that's not the issue. It seems like a simple hack that was not thought through completely and I certainly won't merge it as is. IMHO the things mentioned in the comment in internal.c below the single hunk needs to be addressed first. I am not sure ATM what that even means and won't look into it soon. Also, I don't think it would even work in its current form (no programmer registration happens there that was introduced since the original patch)... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1901 - trunk
by repository service 22 Nov '15

22 Nov '15

Author: stefanct Date: Sun Nov 22 03:23:31 2015 New Revision: 1901 URL: http://flashrom.org/trac/flashrom/changeset/1901 Log: Add support for SST SST25WF020A, SST25WF040B, SST25WF080B. Apart from the strange ID (using Sanyo's vendor ID 0x62) the main difference from the plain SST25WF series is that they lack op codes 0xAD (AAI Word program) and 0x52 (32K erase). The smallest version does not support dual I/O operations either. SST25WF080B was tested under Linux with spidev. Tested-by: Ben Gardner <bgardner(a)wabtec.com> Signed-off-by: Ben Gardner <bgardner(a)wabtec.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/chipdrivers.h trunk/flashchips.c trunk/flashchips.h trunk/spi25_statusreg.c Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Sun Nov 22 00:35:47 2015 (r1900) +++ trunk/chipdrivers.h Sun Nov 22 03:23:31 2015 (r1901) @@ -72,6 +72,7 @@ int spi_prettyprint_status_register_bp3_srwd(struct flashctx *flash); int spi_prettyprint_status_register_bp4_srwd(struct flashctx *flash); int spi_prettyprint_status_register_bp2_bpl(struct flashctx *flash); +int spi_prettyprint_status_register_bp2_tb_bpl(struct flashctx *flash); int spi_disable_blockprotect(struct flashctx *flash); int spi_disable_blockprotect_bp1_srwd(struct flashctx *flash); int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Nov 22 00:35:47 2015 (r1900) +++ trunk/flashchips.c Sun Nov 22 03:23:31 2015 (r1901) @@ -11857,6 +11857,111 @@ { .vendor = "SST", + .name = "SST25WF020A", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, /* See flashchips.h */ + .model_id = SST_SST25WF020A, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {1650, 1950}, + }, + + { + .vendor = "SST", + .name = "SST25WF040B", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, /* See flashchips.h */ + .model_id = SST_SST25WF040B, + .total_size = 512, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual O (0x3B), dual I/O read (0xBB) supported */ + .voltage = {1650, 1950}, + }, + + { + .vendor = "SST", + .name = "SST25WF080B", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, /* See flashchips.h */ + .model_id = SST_SST25WF080B, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual O (0x3B), dual I/O read (0xBB) supported */ + .voltage = {1650, 1950}, + }, + + { + .vendor = "SST", .name = "SST25VF080B", .bustype = BUS_SPI, .manufacture_id = SST_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sun Nov 22 00:35:47 2015 (r1900) +++ trunk/flashchips.h Sun Nov 22 03:23:31 2015 (r1901) @@ -670,11 +670,12 @@ #define SST_SST25WF020 0x2503 #define SST_SST25WF040 0x2504 #define SST_SST25WF080 0x2505 -/* There exist some successors to members of the SST25WF family with alphabetic suffixes. They have very weird - * IDs and were not spotted in the wild yet. Their datasheets show a 4 byte long response w/o a vendor ID. */ -#define SST_SST25WF020A /* 0x62 0x16 0x12 0x00 */ -#define SST_SST25WF040B /* 0x62 0x16 0x13 0x00 */ -#define SST_SST25WF080B /* 0x62 0x16 0x14 0x00 */ +/* There exist some successors to members of the SST25WF family with alphabetic suffixes. Their datasheets show + * a 4 byte long response w/o a vendor ID. The first byte is 0x62 that is actually Sanyo's and might be due to + * a collaboration in the mid 2000ies between Sanyo and SST. */ +#define SST_SST25WF020A 0x1612 +#define SST_SST25WF040B 0x1613 +#define SST_SST25WF080B 0x1614 #define SST_SST25VF512_REMS 0x48 /* REMS or RES opcode, same as SST25VF512A */ #define SST_SST25VF010_REMS 0x49 /* REMS or RES opcode, same as SST25VF010A */ #define SST_SST25VF020_REMS 0x43 /* REMS or RES opcode, same as SST25LF020A */ Modified: trunk/spi25_statusreg.c ============================================================================== --- trunk/spi25_statusreg.c Sun Nov 22 00:35:47 2015 (r1900) +++ trunk/spi25_statusreg.c Sun Nov 22 03:23:31 2015 (r1901) @@ -374,6 +374,19 @@ return 0; } +int spi_prettyprint_status_register_bp2_tb_bpl(struct flashctx *flash) +{ + uint8_t status = spi_read_status_register(flash); + spi_prettyprint_status_register_hex(status); + + spi_prettyprint_status_register_bpl(status); + spi_prettyprint_status_register_bit(status, 6); + msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top"); + spi_prettyprint_status_register_bp(status, 2); + spi_prettyprint_status_register_welwip(status); + return 0; +} + /* === Amic === * FIXME: spi_disable_blockprotect is incorrect but works fine for chips using * spi_prettyprint_status_register_bp1_srwd or

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Re: [flashrom] Winbond flash chip "W39V080FA" (1024 kB, FWH)
by Stefan Tauner 22 Nov '15

22 Nov '15

On Sun, 22 Nov 2015 00:37:20 +0100 "Fabian Hoffmann" <fab1997(a)gmx.net> wrote: > Habe seit kurzem ein neues Mainboard und kann den Command deshalb leider nicht ausführen. Das alte MB funktioniert aber noch. OK, if you ever happen to start it up again please think of flashrom ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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SST49LF040B
by Rikard Åhlund 22 Nov '15

22 Nov '15

Flash Chip : SST49LF040B Mainboard : NF-M2S (Acer E380) Erase And Write Tested and working

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CHIPSET: ASRock N68C-S UCC
by Alexey Belyaev 21 Nov '15

21 Nov '15

Здравствуйте, Flashrom. BIOS image was readed successfully! http://www.asrock.com/mb/NVIDIA/N68C-S%20UCC/index.ru.asp $ lspci 00:00.0 RAM memory: NVIDIA Corporation MCP61 Host Bridge (rev a1) 00:01.0 ISA bridge: NVIDIA Corporation MCP61 LPC Bridge (rev a2) 00:01.1 SMBus: NVIDIA Corporation MCP61 SMBus (rev a2) 00:01.2 RAM memory: NVIDIA Corporation MCP61 Memory Controller (rev a2) 00:02.0 USB controller: NVIDIA Corporation MCP61 USB 1.1 Controller (rev a3) 00:02.1 USB controller: NVIDIA Corporation MCP61 USB 2.0 Controller (rev a3) 00:04.0 PCI bridge: NVIDIA Corporation MCP61 PCI bridge (rev a1) 00:05.0 Audio device: NVIDIA Corporation MCP61 High Definition Audio (rev a2) 00:06.0 IDE interface: NVIDIA Corporation MCP61 IDE (rev a2) 00:07.0 Bridge: NVIDIA Corporation MCP61 Ethernet (rev a2) 00:08.0 IDE interface: NVIDIA Corporation MCP61 SATA Controller (rev a2) 00:08.1 IDE interface: NVIDIA Corporation MCP61 SATA Controller (rev a2) 00:09.0 PCI bridge: NVIDIA Corporation MCP61 PCI Express bridge (rev a2) 00:0b.0 PCI bridge: NVIDIA Corporation MCP61 PCI Express bridge (rev a2) 00:0c.0 PCI bridge: NVIDIA Corporation MCP61 PCI Express bridge (rev a2) 00:0d.0 VGA compatible controller: NVIDIA Corporation C61 [GeForce 7025 / nForce 630a] (rev a2) 00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 01:08.0 Network controller: Ralink corp. RT5360 Wireless 802.11n 1T/1R 01:0a.0 Ethernet controller: Intel Corporation 82545GM Gigabit Ethernet Controller (rev 04) 02:00.0 Network controller: Qualcomm Atheros AR9485 Wireless Network Adapter (rev 01) 03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 06) -- С уважением, Alexey mailto:spider@spider.vc

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Re: [flashrom] Flash chip/chipset not found
by Stefan Tauner 21 Nov '15

21 Nov '15

Hi Mark, thanks for the testing! We have merged the patch with r1900 now and marked the chipset as supported. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Winbond flash chip "W39V080FA" (1024 kB, FWH)
by Stefan Tauner 21 Nov '15

21 Nov '15

On Tue, 3 Nov 2015 14:47:37 +0100 "Fabian Hoffmann" <fab1997(a)gmx.net> wrote: > Hello, you may be interested on the following log. > My system: > OS: Arch Linux 64-Bit > Mainboard: ASUS P5LD2-VM/S 4.00g (MAXDATA OEM-Board, pretty rare I think. It is not listed on the ASUS page.) > CPU: Intel Core 2 Duo E4400 @ 2 GHz > > Flash read went almost fine, I was able to extract the bootlogo out of the rom file, but the MD5 hash sum of the rom file didn't match with an original rom file. Hi Fabian, you should be able to use the code that supports other versions of the P5LD2-VM mainboard to enable writing. Something like this: flashrom --programmer internal:mainboard="ASUS:P5LD2-VM DH" -w modded0404.rom -o ./flashrom-write.txt Should work, I think. Can you please provide us with the output of the following command so that we can add auto-detection for your version too. lspci -nnxxxvv The MD5 mismatch might be normal. The BIOS might use the flash memory as persistent storage area... that is common nowadays. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1900 - trunk
by repository service 21 Nov '15

21 Nov '15

Author: stefanct Date: Sun Nov 22 00:35:47 2015 New Revision: 1900 URL: http://flashrom.org/trac/flashrom/changeset/1900 Log: Add support for VIA VT8251. Seems to work on IBM SurePOS 700 and IBM (now Toshiba) AnyPlace Kiosk Model 4838-310. Tested-by: Jason Vannest <Jason_Vannest(a)abercrombie.com> Tested-by: Rowlinson Mark <Mark.Rowlinson(a)uk.fujitsu.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sat Nov 14 03:55:22 2015 (r1899) +++ trunk/chipset_enable.c Sun Nov 22 00:35:47 2015 (r1900) @@ -1582,6 +1582,7 @@ {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x}, {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x}, {0x1106, 0x3227, OK, "VIA", "VT8237(R)", enable_flash_vt823x}, + {0x1106, 0x3287, OK, "VIA", "VT8251", enable_flash_vt823x}, {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},

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Asus M2N-MX/DVI2
by Лисовой Игорь 21 Nov '15

21 Nov '15

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flashrom November 2015