all 1's - parity violation - No EEPROM/flash device found - compare_id: id1 0xff, id2 0xffff for *every* device tested

[James Feeney]

Where to look for a cause?

I have an only partially booting coreboot firmware image on a Geminilake Chromebook, apparently with a bad payload, but the flash device is obviously being read on boot, as can be seen on the AP console.

Short version: Chromebook boot can read the flash device, but flashrom, through SuzyQable, only reads all "1's".


Have a sparkfun SuzyQable connected to an Arch Linux box, and to the Chromebook.

Have the desired result after running on the Cr50 console:
> ccd reset factory
> ccd testlab enable
> ccd open

Previously running flashrom from the stock ChromeOS would give 'Found GigaDevice flash chip "GD25LQ128C/GD25LQ128D"'.

I have flashrom from both:

git clone https://chromium.googlesource.com/chromiumos/third_party/flashrom
WARNERROR=no CONFIG_MEC1308=no CONFIG_ENE_LPC=no make

and

git clone https://chromium.googlesource.com/chromiumos/platform/standalone-hdctools
flashrom install

These appear to both act exactly the same.

Then:

sudo ./flashrom -V -p raiden_debug_spi:target=AP

results in "No EEPROM/flash device found",

where:

$ sudo ./flashrom -V -p raiden_debug_spi:target=AP |sed -n 's/.*\(compare.*\)/\1/p'|sort|uniq
compare_id: id1 0xff, id2 0xff
compare_id: id1 0xff, id2 0xffff

From running flashrom, the Cr50 console says:

[10398.332186 enable_spi_pinmux: AP]
[10398.445490 usb_spi_board_disable]
[10399.512358 AP UART on]
[10399.514036 CCD state: UARTAP+TX UARTEC+TX I2C SPI USBEC+TX]
[10399.728811 deferred_tpm_rst_isr]
[10399.730025 AP on]
[10399.730757 tpm_reset_request(0, 0)]
[10399.731775 tpm_reset_now(0)]
[10399.735335 tpm_init]
tpm_manufactured: manufactured
[10399.737601 tpm_reset_now: done]
[10402.488852 PinWeaver: Loading Tree!]
[10402.511275 PinWeaver: Loaded Tree. restart_count = 88]
[10402.513121 Skipping commit]
[10402.738718 Committing NVMEM changes.]

This causes the Chromebook to boot, so then:

[10408.218302 power button pressed]
[10408.355704 tpm_rst_asserted]
[10409.356714 AP off]
[10418.538157 AP UART off]
[10418.540362 CCD state: UARTEC+TX I2C SPI USBEC+TX]


I don't know whether or not there should be a report of "usb_spi_board_enable" being called, but it is conspicuously not seen.

If I understand, it appears as if flashrom reads and caches the flash device ID, but is just seeing all "1's".

So - where is the problem? ... the flash device? the "pinmux" accessing the flash? the SPI channel? the USB channel? the Cr50? the raiden_debug_spi driver? some Cr50 configuration variable? some nasty hardware problem?


I did run-across this odd thread:

https://groups.google.com/a/chromium.org/g/chromium-os-discuss/c/yFevUZz9aac

where running flashrom first gives "No EEPROM/flash device found", but subsequently reports, in that case, "Found Winbond flash chip "W25Q256JV_M" (32768 kB, SPI) on raiden_debug_spi."  But, the reason for the different consecutive responses from flashrom were not explored there.


Any thoughts about why the boot process can read the flash device, while flashrom only reads "1's" for the device ID?

I did try running flashrom while specifying the device and forcing a read, but again, it just sees all "1's".


Thanks
James