Attention is currently required from: Angel Pons, qianfan.
Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70529 )
Change subject: Add initial CH347T SPI programmer ......................................................................
Patch Set 6:
(8 comments)
File ch347t_spi.c:
https://review.coreboot.org/c/flashrom/+/70529/comment/45ae4f2a_9ec4cb13 PS2, Line 34: CH347_CMD_SPI_CONTROL,
Yes
Done
File ch347t_spi.c:
https://review.coreboot.org/c/flashrom/+/70529/comment/c7f4f0f0_e7738933 PS3, Line 119: SPI_NSS_HARD
OK, I will change it to SPI_NSS_SOFT, as same as the vendor drivers.
Done
https://review.coreboot.org/c/flashrom/+/70529/comment/df2da099_1b222b41 PS3, Line 330: ch347t_spi_spi_send_command
The two "spi"s are redundant
Done
https://review.coreboot.org/c/flashrom/+/70529/comment/fa4b5ed6_a962d4f0 PS3, Line 367: libusb_release_interface(handle, 0); : libusb_attach_kernel_driver(handle, 0);
Interface 2, see comment in `ch347t_spi_init`
Done
https://review.coreboot.org/c/flashrom/+/70529/comment/4fa9ebae_bd022a84 PS3, Line 420: 0
Got it. I will make a change.
Done
https://review.coreboot.org/c/flashrom/+/70529/comment/2c08c511_e814bc65 PS3, Line 425: 0
Interface 2
Done
https://review.coreboot.org/c/flashrom/+/70529/comment/8c035452_b111ba34 PS3, Line 442: release_interface: : libusb_release_interface(handle, 0); : close_handle: : libusb_attach_kernel_driver(handle, 0);
Interface 2
Done
File ch347t_spi.c:
https://review.coreboot.org/c/flashrom/+/70529/comment/1410baf4_05f1659b PS5, Line 169: if (n > CH347_MAX_DATA_WRITE) : n = CH347_MAX_DATA_WRITE;
Oh wait, this is chunking the transfers, right? It's a bit confusing because the chunk size goes thr […]
Yes, I believe this code is for splitting up transfers into smaller transfers. I did basically the same thing in my code. Looks like there is a `min()` function in `helpers.c`, which is declared in the `flash.h` header file (which is already included)
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Nicholas Chin (Code Review)