Change in flashrom[master]: sb600spi.c: Fix for 0x790b rev 0x61

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Fix for 0x790b rev 0x61
......................................................................

sb600spi.c: Fix for 0x790b rev 0x61

Adds support for rev 0x61 of pid 0x790b. Note that the
read callback requires a memory mapping.

Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b
Signed-off-by: Edward O'Callaghan 
---
M sb600spi.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/44073/1

diff --git a/sb600spi.c b/sb600spi.c
index 5892d57..d879281 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -76,7 +76,7 @@
    .max_data_write = FIFO_SIZE_YANGTZE - 3,
    .command = spi100_spi_send_command,
    .multicommand = default_spi_send_multicommand,
-	.read = default_spi_read,
+	.read = read_memmapped,
    .write_256 = default_spi_write_256,
    .write_aai = default_spi_write_aai,
 };
@@ -143,7 +143,7 @@
    	if (rev == 0x4a) {
    		amd_gen = CHIPSET_YANGTZE;
    		msg_pdbg("Yangtze detected.\n");
-		} else if (rev == 0x4b) {
+		} else if (rev == 0x4b || rev == 0x61) {
    		amd_gen = CHIPSET_PROMONTORY;
    		msg_pdbg("Promontory detected.\n");
    	} else {

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Fix for 0x790b rev 0x61
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/flashrom/+/44073/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/44073/1//COMMIT_MSG@7 
PS1, Line 7: 0x790b rev 0x61
Does this device have a prettier name?

https://review.coreboot.org/c/flashrom/+/44073/1//COMMIT_MSG@9 
PS1, Line 9: Note that the
           : read callback requires a memory mapping.
Why does read now require memory mapping? Does it affect original Yangtze?

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Fix for 0x790b rev 0x61
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/flashrom/+/44073/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/44073/1//COMMIT_MSG@7 
PS1, Line 7: 0x790b rev 0x61
> Does this device have a prettier name?

I think just Ryzen? I barely follow all the marketing names now.

https://review.coreboot.org/c/flashrom/+/44073/1//COMMIT_MSG@9 
PS1, Line 9: Note that the
           : read callback requires a memory mapping.
> Why does read now require memory mapping? Does it affect original Yangtze?

It doesn't work without it? Unfortunately cros just doesn't have the quality of commit message that we have here so it is hard to find the historical context.

As far as I am aware this doesn't regress although I do not have the precise hardware to confirm.

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Fix for 0x790b rev 0x61
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/flashrom/+/44073/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/44073/1//COMMIT_MSG@7 
PS1, Line 7: 0x790b rev 0x61
> I think just Ryzen? I barely follow all the marketing names now.

https://www.mail-archive.com/[e-mail]/msg14352.html
https://www.mail-archive.com/[e-mail]/msg14232.html

I suppose AMD calls it "AMD FP4" or "Raven/Raven2" which are essentially other marketing names for Ryzen.

Change in flashrom[master]: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]

[Edward O'Callaghan (Code Review)]

Hello build bot (Jenkins), Nico Huber, Martin Roth, Angel Pons, Kangheui Won,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/44073

to look at the new patch set (#2).

Change subject: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]
......................................................................

sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]

Adds support for rev 0x61 of pid 0x790b. Note that the
read callback requires a memory mapping.

Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b
Signed-off-by: Edward O'Callaghan 
---
M sb600spi.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/44073/2

Change in flashrom[master]: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]
......................................................................

Patch Set 2: Code-Review+1

Change in flashrom[master]: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/flashrom/+/44073/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/44073/1//COMMIT_MSG@7 
PS1, Line 7: 0x790b rev 0x61
> https://www.mail-archive.com/[e-mail]/msg14352.html […]

Ack

Change in flashrom[master]: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]

[Kangheui Won (Code Review)]

Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]
......................................................................

Patch Set 2: Code-Review+1

Change in flashrom[master]: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]
......................................................................

Patch Set 2: Code-Review+2

Change in flashrom[master]: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]
......................................................................

Patch Set 2: Code-Review-1

-1 for now until I can get to the bottom of the read_memmapped() callback change. I still feel this is covering up from a deeper issue somewhere.

Change in flashrom[master]: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Fix for 0x790b AMD FP4 [rev 0x61]
......................................................................

Patch Set 2: Code-Review+1

[Edward O'Callaghan (Code Review)]

Hello build bot (Jenkins), Nico Huber, Martin Roth, Kangheui Won, Angel Pons, Chris McDonald, Kangheui Won,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/44073

to look at the new patch set (#3).

Change subject: sb600spi.c: Fix for 0x790b rev 0x61
......................................................................

sb600spi.c: Fix for 0x790b rev 0x61

Adds support for rev 0x61 of pid 0x790b. Note that the
read callback requires a memory mapping.

Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b
Signed-off-by: Edward O'Callaghan 
---
M sb600spi.c
1 file changed, 40 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/44073/3

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

Set Ready For Review

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Edward O'Callaghan (Code Review)]

Hello Daniel Kurtz, build bot (Jenkins), Nico Huber, Martin Roth, Kangheui Won, Angel Pons, Chris McDonald, Kangheui Won,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/44073

to look at the new patch set (#6).

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

Adds support for rev 0x59 || 0x61 of did 0x790b.

This is quite confusing however it turns out FCH chipsets
called 'Promontory' are one's with the so-called SPI100 ip
core that uses memory mapping and not a ring buffer for
transactions. Typically this is found on both Stoney Ridge
and Zen platforms. In light of this, seperate out the
promontory path into it's own callback struct state tracker
so that it's implementation does not interfere with previous
generations that predate the SPI100 controller.

Since there is some lift-time state required to track the mapping
during between the first attempted read and the final tear-down of
the spi master we take the opportunity to avoid static locals and
instead implement the functionality in a re-enterent way for follow
up clean ups.

BUG=none
BRANCH=none
TEST=none

Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b
Signed-off-by: Edward O'Callaghan 
---
M sb600spi.c
1 file changed, 63 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/44073/6

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Edward O'Callaghan (Code Review)]

Hello Daniel Kurtz, build bot (Jenkins), Nico Huber, Martin Roth, Kangheui Won, Angel Pons, Chris McDonald, Kangheui Won,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/44073

to look at the new patch set (#7).

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

Adds support for rev 0x59 || 0x61 of did 0x790b.

This is quite confusing however it turns out FCH chipsets
called 'Promontory' are one's with the so-called SPI100 ip
core that uses memory mapping and not a ring buffer for
transactions. Typically this is found on both Stoney Ridge
and Zen platforms. In light of this, seperate out the
promontory path into it's own callback struct state tracker
so that it's implementation does not interfere with previous
generations that predate the SPI100 controller.

Since there is some lift-time state required to track the mapping
during between the first attempted read and the final tear-down of
the spi master we take the opportunity to avoid static locals and
instead implement the functionality in a re-enterent way for follow
up clean ups.

BUG=none
BRANCH=none
TEST=none

Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b
Signed-off-by: Edward O'Callaghan 
---
M sb600spi.c
1 file changed, 64 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/44073/7

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Edward O'Callaghan (Code Review)]

Hello Daniel Kurtz, build bot (Jenkins), Nico Huber, Martin Roth, Kangheui Won, Angel Pons, Chris McDonald, Kangheui Won,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/44073

to look at the new patch set (#8).

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

Adds support for rev 0x59 || 0x61 of did 0x790b.

This is quite confusing however it turns out FCH chipsets
called 'Promontory' are one's with the so-called SPI100 ip
core that uses memory mapping and not a ring buffer for
transactions. Typically this is found on both Stoney Ridge
and Zen platforms. In light of this, seperate out the
promontory path into it's own callback struct state tracker
so that it's implementation does not interfere with previous
generations that predate the SPI100 controller.

Since there is some lift-time state required to track the mapping
during between the first attempted read and the final tear-down of
the spi master we take the opportunity to avoid static locals and
instead implement the functionality in a re-enterent way for follow
up clean ups.

BUG=none
BRANCH=none
TEST= Zork => 'Promontory (rev 0x61) detected.' &&
     Grunt => 'Promontory (rev 0x4b) detected.'

Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b
Signed-off-by: Edward O'Callaghan 
---
M sb600spi.c
1 file changed, 64 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/44073/8

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

Patch Set 8: Code-Review+1

(5 comments)

https://review.coreboot.org/c/flashrom/+/44073/8//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/44073/8//COMMIT_MSG@12 
PS8, Line 12: are one's with
Huh?

https://review.coreboot.org/c/flashrom/+/44073/8//COMMIT_MSG@15 
PS8, Line 15: seperate
sep*a*rate

https://review.coreboot.org/c/flashrom/+/44073/8//COMMIT_MSG@16 
PS8, Line 16: it's
its

https://review.coreboot.org/c/flashrom/+/44073/8//COMMIT_MSG@20 
PS8, Line 20: lift-time
huh?

https://review.coreboot.org/c/flashrom/+/44073/8//COMMIT_MSG@23 
PS8, Line 23: enterent
entrant

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Edward O'Callaghan (Code Review)]

Hello Daniel Kurtz, build bot (Jenkins), Nico Huber, Martin Roth, Kangheui Won, Angel Pons, Chris McDonald, Kangheui Won,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/44073

to look at the new patch set (#9).

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

Adds support for rev 0x59 || 0x61 of did 0x790b.

This is quite confusing however it turns out FCH chipsets
called 'Promontory' contain the so-called SPI100 ip
core that uses memory mapping and not a ring buffer for
transactions. Typically this is found on both Stoney Ridge
and Zen platforms. In light of this, separate out the
promontory path into its own callback struct state tracker
so that it's implementation does not interfere with previous
generations that predate the SPI100 controller.

Since there is some life-time state required to track the mapping
during between the first attempted read and the final tear-down of
the spi master we take the opportunity to avoid static locals and
instead implement the functionality in a re-entrant way for follow
up clean ups.

BUG=none
BRANCH=none
TEST= Zork => 'Promontory (rev 0x61) detected.' &&
     Grunt => 'Promontory (rev 0x4b) detected.'

Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b
Signed-off-by: Edward O'Callaghan 
---
M sb600spi.c
1 file changed, 64 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/44073/9

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

Patch Set 9:

(5 comments)

https://review.coreboot.org/c/flashrom/+/44073/8//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/44073/8//COMMIT_MSG@12 
PS8, Line 12: are one's with
> Huh?

Done

https://review.coreboot.org/c/flashrom/+/44073/8//COMMIT_MSG@15 
PS8, Line 15: seperate
> sep*a*rate

Done

https://review.coreboot.org/c/flashrom/+/44073/8//COMMIT_MSG@16 
PS8, Line 16: it's
> its

Done

https://review.coreboot.org/c/flashrom/+/44073/8//COMMIT_MSG@20 
PS8, Line 20: lift-time
> huh?

Done

https://review.coreboot.org/c/flashrom/+/44073/8//COMMIT_MSG@23 
PS8, Line 23: enterent
> entrant

Done

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Sam McNally (Code Review)]

Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

Patch Set 9:

(1 comment)

https://review.coreboot.org/c/flashrom/+/44073/9/sb600spi.c 
File sb600spi.c:

https://review.coreboot.org/c/flashrom/+/44073/9/sb600spi.c@591 
PS9, Line 591: MAX_DATA_WRITE_UNLIMITED
FIFO_SIZE_YANGTZE - 3

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Edward O'Callaghan (Code Review)]

Hello Daniel Kurtz, build bot (Jenkins), Nico Huber, Martin Roth, Kangheui Won, Angel Pons, Chris McDonald, Kangheui Won,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/44073

to look at the new patch set (#10).

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

Adds support for rev 0x59 || 0x61 of did 0x790b.

This is quite confusing however it turns out FCH chipsets
called 'Promontory' contain the so-called SPI100 ip
core that uses memory mapping and not a ring buffer for
transactions. Typically this is found on both Stoney Ridge
and Zen platforms. In light of this, separate out the
promontory path into its own callback struct state tracker
so that it's implementation does not interfere with previous
generations that predate the SPI100 controller.

Since there is some life-time state required to track the mapping
during between the first attempted read and the final tear-down of
the spi master we take the opportunity to avoid static locals and
instead implement the functionality in a re-entrant way for follow
up clean ups.

BUG=none
BRANCH=none
TEST= Zork => 'Promontory (rev 0x61) detected.' &&
     Grunt => 'Promontory (rev 0x4b) detected.'

Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b
Signed-off-by: Edward O'Callaghan 
---
M sb600spi.c
1 file changed, 64 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/44073/10

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

Patch Set 10:

(1 comment)

https://review.coreboot.org/c/flashrom/+/44073/9/sb600spi.c 
File sb600spi.c:

https://review.coreboot.org/c/flashrom/+/44073/9/sb600spi.c@591 
PS9, Line 591: MAX_DATA_WRITE_UNLIMITED
> FIFO_SIZE_YANGTZE - 3

Done

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

Patch Set 10:

(1 comment)

https://review.coreboot.org/c/flashrom/+/44073/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/44073/1//COMMIT_MSG@9 
PS1, Line 9: Note that the
           : read callback requires a memory mapping.
> It doesn't work without it? Unfortunately cros just doesn't have the quality of commit message that  […]

Resolved now that the paths have been appropriately split and a little more is known about the SPI100 controller.

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Sam McNally (Code Review)]

Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

Patch Set 10: Code-Review+2

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

Adds support for rev 0x59 || 0x61 of did 0x790b.

This is quite confusing however it turns out FCH chipsets
called 'Promontory' contain the so-called SPI100 ip
core that uses memory mapping and not a ring buffer for
transactions. Typically this is found on both Stoney Ridge
and Zen platforms. In light of this, separate out the
promontory path into its own callback struct state tracker
so that it's implementation does not interfere with previous
generations that predate the SPI100 controller.

Since there is some life-time state required to track the mapping
during between the first attempted read and the final tear-down of
the spi master we take the opportunity to avoid static locals and
instead implement the functionality in a re-entrant way for follow
up clean ups.

BUG=none
BRANCH=none
TEST= Zork => 'Promontory (rev 0x61) detected.' &&
     Grunt => 'Promontory (rev 0x4b) detected.'

Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b
Signed-off-by: Edward O'Callaghan 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/44073
Tested-by: build bot (Jenkins) 
Reviewed-by: Sam McNally 
---
M sb600spi.c
1 file changed, 64 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Sam McNally: Looks good to me, approved

diff --git a/sb600spi.c b/sb600spi.c
index 40434f0..2e27cee 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -55,6 +55,10 @@
 #define FIFO_SIZE_OLD		8
 #define FIFO_SIZE_YANGTZE	71

+struct sb600spi_data {
+	struct flashctx *flash;
+};
+
 static int find_smbus_dev_rev(uint16_t vendor, uint16_t device)
 {
    struct pci_dev *smbus_dev = pci_dev_find(vendor, device);
@@ -116,8 +120,17 @@
    	if (rev == 0x4a) {
    		msg_pdbg("Yangtze detected.\n");
    		return CHIPSET_YANGTZE;
-		} else if (rev == 0x4b) {
-			msg_pdbg("Promontory detected.\n");
+		/**
+		 * FCH chipsets called 'Promontory' are one's with the
+		 * so-called SPI100 ip core that uses memory mapping and
+		 * not a ring buffer for transactions. Typically this is
+		 * found on both Stoney Ridge and Zen platforms.
+		 *
+		 * The revisions I have found by searching various lspci
+		 * outputs are as follows: 0x4b, 0x59 & 0x61.
+		 */
+		} else if (rev == 0x4b || rev == 0x59 || rev == 0x61) {
+			msg_pdbg("Promontory (rev 0x%02x) detected.\n", rev);
    		return CHIPSET_PROMONTORY;
    	} else {
    		msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n"
@@ -541,6 +554,18 @@
    return amd_imc_shutdown(dev);
 }

+static int promontory_read_memmapped(struct flashctx *flash, uint8_t *buf,
+		unsigned int start, unsigned int len)
+{
+	struct sb600spi_data * data = (struct sb600spi_data *)flash->mst->spi.data;
+	if (!data->flash) {
+		map_flash(flash);
+		data->flash = flash; /* keep a copy of flashctx for unmap() on tear-down. */
+	}
+	mmio_readn((void *)(flash->virtual_memory + start), buf, len);
+	return 0;
+}
+
 static struct spi_master spi_master_sb600 = {
    .max_data_read = FIFO_SIZE_OLD,
    .max_data_write = FIFO_SIZE_OLD - 3,
@@ -561,6 +586,25 @@
    .write_aai = default_spi_write_aai,
 };

+static struct spi_master spi_master_promontory = {
+	.max_data_read = MAX_DATA_READ_UNLIMITED,
+	.max_data_write = FIFO_SIZE_YANGTZE - 3,
+	.command = spi100_spi_send_command,
+	.multicommand = default_spi_send_multicommand,
+	.read = promontory_read_memmapped,
+	.write_256 = default_spi_write_256,
+	.write_aai = default_spi_write_aai,
+};
+
+static int sb600spi_shutdown(void *data)
+{
+	struct flashctx *flash = ((struct sb600spi_data *)data)->flash;
+	if (flash)
+		finalize_flash_access(flash);
+	free(data);
+	return 0;
+}
+
 int sb600_probe_spi(struct pci_dev *dev)
 {
    struct pci_dev *smbus_dev;
@@ -726,11 +770,28 @@
    if (handle_imc(dev, amd_gen) != 0)
    	return ERROR_FATAL;

+	struct sb600spi_data *data = calloc(1, sizeof(struct sb600spi_data));
+	if (!data) {
+		msg_perr("Unable to allocate space for extra SPI master data.\n");
+		return SPI_GENERIC_ERROR;
+	}
+
+	data->flash = NULL;
+
+	register_shutdown(sb600spi_shutdown, data);
+	spi_master_sb600.data = data;
+	spi_master_yangtze.data = data;
+	spi_master_promontory.data = data;
+
+
    /* Starting with Yangtze the SPI controller got a different interface with a much bigger buffer. */
    if (amd_gen < CHIPSET_YANGTZE)
    	register_spi_master(&spi_master_sb600);
-	else
+	else if (amd_gen == CHIPSET_YANGTZE)
    	register_spi_master(&spi_master_yangtze);
+	else
+		register_spi_master(&spi_master_promontory);
+
    return 0;
 }

Change in flashrom[master]: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44073 )

Change subject: sb600spi.c: Add support for 0x790b rev 0x61 (AMD Zen)
......................................................................

Patch Set 11:

(1 comment)

https://review.coreboot.org/c/flashrom/+/44073/11//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/44073/11//COMMIT_MSG@28 
PS11, Line 28: Zork => 'Promontory
this is misleading. the code paths should be right though