Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian, Felix Held. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63422 )
Change subject: sb600spi.c: Use SPI100 bit mappings ......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/63422/comment/5ce3caa2_3038c36e PS1, Line 8: : Flashrom has been using legacy spi100 bit mappings when programming the : opcode and triggering the command. These legacy bit mappings are : deprecated in upcoming generation of AMD SoCs. The knowledge of how SPI100 works completely is spare, can you provide more precise details here?
https://review.coreboot.org/c/flashrom/+/63422/comment/c3c35fa1_8b60cc3d PS1, Line 11: Stop using the legacy : spi100 registers and use the correct ones. Is this backwards compatiable with all chipsets that find their way onto these specific branches of `spi100_spi_send_command()`?
Can you test the earlier chipsets to ensure we do not regress them?
File sb600spi.c:
https://review.coreboot.org/c/flashrom/+/63422/comment/e4324960_065d4b0a PS1, Line 574: promontory_read_memmapped( does this patch allow for this hack to be removed?
It would be useful to know precisely why this was needed on newer AMD spi controllers to make it work^tm?
The following maybe co-related: https://review.coreboot.org/c/flashrom/+/58776 https://review.coreboot.org/c/flashrom/+/58777 but need some attention and coordination of a board owner.
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Edward O'Callaghan (Code Review)