[XS] Change in flashrom[main]: flashchips: Add GD25Q128E name to the GD25Q127C/GD25Q128C entry

[Anastasia Klimchuk (Code Review)]

Attention is currently required from: Hsuan-ting Chen, Nikolai Artemiev, Stefan Reinauer.

Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/78348?usp=email )

Change subject: flashchips: Add GD25Q128E name to the GD25Q127C/GD25Q128C entry
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Patch Set 2:

(2 comments)

File flashchips.c:

https://review.coreboot.org/c/flashrom/+/78348/comment/93f859e3_7b14fbbd :
PS1, Line 6802: /* FIXME: 128E's OTP: 3072B total and doesn't support QPI */
> I have two questions about these: […]

1. Yes, I think you need to separate the two chip definitions. This is what I meant when I said you need to split. You can copypaste existing definition into new one, make necessary changes and adjustments, and put new the one in alphabetical order.
At the end there will be two definitions instead of one that it now.
Also you will need to update the commit title.

2. If there are 3 different chips with the same IDs, you will need to provide chip name with `-c` or `--chip` options (you can check this option on man page which is also on the web page https://flashrom.org/classic_cli_manpage.html#options)

https://review.coreboot.org/c/flashrom/+/78348/comment/78a3141c_58c89996 :
PS1, Line 6833: .reg_bits	=
              : 		{
              : 			.srp    = {STATUS1, 7, RW},
              : 			.srl    = {STATUS2, 0, RW},
              : 			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
              : 			.tb     = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
              : 			.sec    = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */
              : 			.cmp    = {STATUS2, 6, RW},
              : 		}
> > Are all these registers the same for new chip you are adding […]

Great thank you!