Change in flashrom[master]: raiden_debug_spi.c: Add a delay following AP/EC flash enable
Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39312 )
Change subject: raiden_debug_spi.c: Add a delay following AP/EC flash enable ......................................................................
raiden_debug_spi.c: Add a delay following AP/EC flash enable
Add a delay following the AP and EC flash enable requests. This allows any power rails enabled by these signals to settle and to meet the power on to first SPI write timing requirements.
Forward ports the downstream commit: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+...
Change-Id: I4c1777777ee67580605c6e6f4c0c228cccc392c7 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M raiden_debug_spi.c 1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/39312/1
diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index fa42268..6914455 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -562,6 +562,15 @@ return ret; }
+ /* + * Allow for power to settle on the AP and EC flash devices. + * Load switches can have a 1-3 ms turn on time, and SPI flash devices + * can require up to 10 ms from power on to the first write. + */ + if ((request_enable == RAIDEN_DEBUG_SPI_REQ_ENABLE_AP) || + (request_enable == RAIDEN_DEBUG_SPI_REQ_ENABLE_EC)) + usleep(50 * 1000); + register_spi_master(&spi_master_raiden_debug); register_shutdown(shutdown, NULL);
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/39312 )
Change subject: raiden_debug_spi.c: Add a delay following AP/EC flash enable ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/flashrom/+/39312/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/flashrom/+/39312/1//COMMIT_MSG@7 PS1, Line 7: One space.
Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/39312 )
Change subject: raiden_debug_spi.c: Add a delay following AP/EC flash enable ......................................................................
Patch Set 1: Code-Review+2
Hello build bot (Jenkins), Stefan Reinauer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/39312
to look at the new patch set (#2).
Change subject: raiden_debug_spi.c: Add a delay following AP/EC flash enable ......................................................................
raiden_debug_spi.c: Add a delay following AP/EC flash enable
Add a delay following the AP and EC flash enable requests. This allows any power rails enabled by these signals to settle and to meet the power on to first SPI write timing requirements.
Forward ports the downstream commit: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+...
Change-Id: I4c1777777ee67580605c6e6f4c0c228cccc392c7 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M raiden_debug_spi.c 1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/39312/2
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/39312 )
Change subject: raiden_debug_spi.c: Add a delay following AP/EC flash enable ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/flashrom/+/39312/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/flashrom/+/39312/1//COMMIT_MSG@7 PS1, Line 7:
One space.
Done
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/39312 )
Change subject: raiden_debug_spi.c: Add a delay following AP/EC flash enable ......................................................................
raiden_debug_spi.c: Add a delay following AP/EC flash enable
Add a delay following the AP and EC flash enable requests. This allows any power rails enabled by these signals to settle and to meet the power on to first SPI write timing requirements.
Forward ports the downstream commit: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+...
Change-Id: I4c1777777ee67580605c6e6f4c0c228cccc392c7 Signed-off-by: Edward O'Callaghan quasisec@google.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/39312 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Stefan Reinauer stefan.reinauer@coreboot.org --- M raiden_debug_spi.c 1 file changed, 9 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved
diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index fa42268..6914455 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -562,6 +562,15 @@ return ret; }
+ /* + * Allow for power to settle on the AP and EC flash devices. + * Load switches can have a 1-3 ms turn on time, and SPI flash devices + * can require up to 10 ms from power on to the first write. + */ + if ((request_enable == RAIDEN_DEBUG_SPI_REQ_ENABLE_AP) || + (request_enable == RAIDEN_DEBUG_SPI_REQ_ENABLE_EC)) + usleep(50 * 1000); + register_spi_master(&spi_master_raiden_debug); register_shutdown(shutdown, NULL);
-
Edward O'Callaghan (Code Review) -
Paul Menzel (Code Review)
-
Stefan Reinauer (Code Review)