Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34073 )
Change subject: chipset_enable: Mark Intel/CM246 as DEP ......................................................................
chipset_enable: Mark Intel/CM246 as DEP
The usual ME-lock limitations apply, so this is DEP instead of OK.
Tested on Siemens/Field PG M6, and also regression tested on Apollo Lake and Skylake. Flashrom works fine, and logs and descriptor dumps look good. Also, register and descriptor output agree on the flash layout and permissions.
Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61 Signed-off-by: Nico Huber nico.huber@secunet.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/34073/1
diff --git a/chipset_enable.c b/chipset_enable.c index 3773158..f75f94d 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2044,7 +2044,7 @@ {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300}, {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, - {0x8086, 0xa30e, B_S, NT, "Intel", "CM246", enable_flash_pch300}, + {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300}, #endif {0}, };
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/34073
to look at the new patch set (#2).
Change subject: chipset_enable: Mark Intel CM236 and CM246 as DEP ......................................................................
chipset_enable: Mark Intel CM236 and CM246 as DEP
The usual ME-lock limitations apply, so this is DEP instead of OK.
Tested on Kontron/bSL6 (SKL) and Siemens/Field PG M6 (CFL) and also regression tested on Apollo Lake. Flashrom works fine, and logs and descriptor dumps look good. Also, register and descriptor output agree on the flash layout and permissions.
Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61 Signed-off-by: Nico Huber nico.huber@secunet.com --- M chipset_enable.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/34073/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/34073 )
Change subject: chipset_enable: Mark Intel CM236 and CM246 as DEP ......................................................................
Patch Set 3: Code-Review+2
Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/flashrom/+/34073 )
Change subject: chipset_enable: Mark Intel CM236 and CM246 as DEP ......................................................................
chipset_enable: Mark Intel CM236 and CM246 as DEP
The usual ME-lock limitations apply, so this is DEP instead of OK.
Tested on Kontron/bSL6 (SKL) and Siemens/Field PG M6 (CFL) and also regression tested on Apollo Lake. Flashrom works fine, and logs and descriptor dumps look good. Also, register and descriptor output agree on the flash layout and permissions.
Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61 Signed-off-by: Nico Huber nico.huber@secunet.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/34073 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M chipset_enable.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/chipset_enable.c b/chipset_enable.c index 1636f7c..f02ba87 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2009,7 +2009,7 @@ {0x8086, 0xa14b, B_S, NT, "Intel", "Sunrise Point Server Sample", enable_flash_pch100}, {0x8086, 0xa14d, B_S, NT, "Intel", "QM170", enable_flash_pch100}, {0x8086, 0xa14e, B_S, NT, "Intel", "HM170", enable_flash_pch100}, - {0x8086, 0xa150, B_S, NT, "Intel", "CM236", enable_flash_pch100}, + {0x8086, 0xa150, B_S, DEP, "Intel", "CM236", enable_flash_pch100}, {0x8086, 0xa151, B_S, NT, "Intel", "QMS180", enable_flash_pch100}, {0x8086, 0xa152, B_S, NT, "Intel", "HM175", enable_flash_pch100}, {0x8086, 0xa153, B_S, NT, "Intel", "QM175", enable_flash_pch100}, @@ -2045,7 +2045,7 @@ {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300}, {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, - {0x8086, 0xa30e, B_S, NT, "Intel", "CM246", enable_flash_pch300}, + {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300}, #endif {0}, };
-
Angel Pons (Code Review) -
Nico Huber (Code Review)