Change in flashrom[master]: chipset_enable.c: Add PCI ID for Comet Lake U Base

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/51401 )

Change subject: chipset_enable.c: Add PCI ID for Comet Lake U Base
......................................................................

chipset_enable.c: Add PCI ID for Comet Lake U Base

TEST=`flashrom -r` on a kindred chromebook with a Celeron 5205U.

Change-Id: I627dcacdad167343287ac0ec26b47505c2f823ee
Signed-off-by: Sam McNally 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51401
Tested-by: build bot (Jenkins) 
Reviewed-by: Edward O'Callaghan 
Reviewed-by: Angel Pons 
---
M chipset_enable.c
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Edward O'Callaghan: Looks good to me, approved

diff --git a/chipset_enable.c b/chipset_enable.c
index 138cb12..d5c10c4 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2020,6 +2020,7 @@
    {0x8086, 0x9d58, B_S,    NT,  "Intel", "Kaby Lake U Premium",		enable_flash_pch100},
    {0x8086, 0x9d84, B_S,    DEP, "Intel", "Cannon Lake U Premium",		enable_flash_pch300},
    {0x8086, 0x0284, B_S,    DEP, "Intel", "Comet Lake U Premium",		enable_flash_pch400},
+	{0x8086, 0x0285, B_S,    DEP, "Intel", "Comet Lake U Base",		enable_flash_pch400},
    {0x8086, 0xa141, B_S,    NT,  "Intel", "Sunrise Point Desktop Sample",	enable_flash_pch100},
    {0x8086, 0xa142, B_S,    NT,  "Intel", "Sunrise Point Unknown Sample",	enable_flash_pch100},
    {0x8086, 0xa143, B_S,    DEP, "Intel", "H110",				enable_flash_pch100},