Change in flashrom[master]: ichspi: Define `Write Enable Type (WET)` register under HSFC

[Nico Huber (Code Review)]

Attention is currently required from: Subrata Banik, Angel Pons.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62888 )

Change subject: ichspi: Define `Write Enable Type (WET)` register under HSFC
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Patch Set 6:

(1 comment)

File ichspi.c:

https://review.coreboot.org/c/flashrom/+/62888/comment/ace760a0_13b4df28 
PS6, Line 91: /* New HSFC Control bit */
> > If you have doubts that the bit was introduced with PCH100, you can always
> > test the hardware.
>
> Do we have any action item here regarding the open comment or we are good here ?

If you think the code should be changed because the bit existed earlier,
you should confirm that by testing the bit on respective hardware. If it
didn't exist earlier, there is nothing to change, I suppose.
> Ref to Intel doc 355845 section 22.1.3. Bit 7:3 are reserved, so, WET bit does exist there.

I can't find that document, what is its title? And I don't understand,
why does it exist when the doc says reserved?