Attention is currently required from: Anastasia Klimchuk, Nicholas Chin.
ZhiYuanNJ has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email )
Change subject: ch347_spi: Add spi clock frequency selection ......................................................................
Patch Set 7:
(4 comments)
File ch347_spi.c:
https://review.coreboot.org/c/flashrom/+/82776/comment/a8b52623_5481dab5?usp... : PS7, Line 357: index = 0
Let's use different variable name, index is already used for indexing the device table. […]
Done
https://review.coreboot.org/c/flashrom/+/82776/comment/cfc81251_9587a9e8?usp... : PS7, Line 365: 30MHz
I don't mind changing the default if it generally works at 30 MHz. […]
What is the CH347T device revision that can reproduce this phenomenon?
https://review.coreboot.org/c/flashrom/+/82776/comment/309c527c_1c462d2e?usp... : PS7, Line 365: Invalid SPI speed
It would be invalid value if you would throw an error and exit, however you do not, but instead cont […]
Done
https://review.coreboot.org/c/flashrom/+/82776/comment/ca2bf3af_a5217846?usp... : PS7, Line 372: clock spi
"clock spi" is redundant here as clock is already mentioned earlier. […]
Done
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ZhiYuanNJ (Code Review)