Change in flashrom[master]: flashchips: add definition of the XT25F02E SPI NOR flash

[Angel Pons (Code Review)]

Attention is currently required from: Neil Armstrong.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/50263 )

Change subject: flashchips: add definition of the XT25F02E SPI NOR flash
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Patch Set 1: Code-Review+1

(3 comments)

Commit Message:

https://review.coreboot.org/c/flashrom/+/50263/comment/e262831f_4f21e27a 
PS1, Line 9: Technology Limited.
nit: put this part on the next line (line length limit for commit messages is 72 characters)

File flashchips.c:

https://review.coreboot.org/c/flashrom/+/50263/comment/fb5e6510_34710e91 
PS1, Line 19242: TEST_UNTESTED
It would be great to test this flash chip, if you can.

https://review.coreboot.org/c/flashrom/+/50263/comment/cf451758_7b364d63 
PS1, Line 19253: , {
               : 				.eraseblocks = { {256 * 1024, 1} },
               : 				.block_erase = spi_block_erase_c7,
               : 			}
Missing one entry for opcode 0x60:

}, {
    .eraseblocks = { {256 * 1024, 1} },
    .block_erase = spi_block_erase_60,
 }

Place it before the entry for opcode 0xc7