Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46064 )
Change subject: WIP: flashchips.c: import chips from cros flashrom ......................................................................
WIP: flashchips.c: import chips from cros flashrom
Signed-off-by: Nikolai Artemiev nartemiev@google.com Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 --- M flashchips.c 1 file changed, 217 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/46064/1
diff --git a/flashchips.c b/flashchips.c index 7d10abf..82dbf70 100644 --- a/flashchips.c +++ b/flashchips.c @@ -15814,6 +15814,68 @@
{ .vendor = "Spansion", + .name = "S25FL128S_UL Uniform 128 kB Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128S_UL, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {128 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FL128S_US Uniform 64 kB Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128S_US, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", .name = "S25FL129P......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, @@ -16038,6 +16100,62 @@
{ .vendor = "Spansion", + .name = "S25FL256S Large Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL256S_UL, + .total_size = 16384, /* This is just half the size.... */ + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {256 * 1024, 64} }, + .block_erase = s25fl_block_erase, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FL256S Small Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL256S_US, + .total_size = 16384, /* This is just half the size.... */ + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fl_block_erase, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", .name = "S25FL256S......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, @@ -16116,6 +16234,68 @@ },
{ + .vendor = "Spansion", + .name = "S25FS128S Large Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FS128S_L, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fs_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FS128S Small Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FS128S_S, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fs_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { .vendor = "SyncMOS/MoselVitelic", .name = "{F,S,V}29C51001B", .bustype = BUS_PARALLEL, @@ -17014,6 +17194,43 @@
{ .vendor = "Winbond", + .name = "W25Q32JW", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q32JW, + .total_size = 4096, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, + }, + + { + .vendor = "Winbond", .name = "W25Q40.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID,
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/46064
to look at the new patch set (#2).
Change subject: WIP: flashchips.c: import chips from cros flashrom ......................................................................
WIP: flashchips.c: import chips from cros flashrom
Signed-off-by: Nikolai Artemiev nartemiev@google.com Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 --- M flashchips.c M flashchips.h 2 files changed, 236 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/46064/2
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/46064 )
Change subject: WIP: flashchips.c: import chips from cros flashrom ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/flashrom/+/46064/2/flashchips.h File flashchips.h:
https://review.coreboot.org/c/flashrom/+/46064/2/flashchips.h@945 PS2, Line 945: /* : * W25Q128 has several variants. Currently all are 3.3V except for the W25Q128FW : * which is 1.8V. Otherwise they should behave the same... : */ : #define WINBOND_NEX_W25Q128_V 0x4018 /* W25Q128BV, W25Q128FV (SPI mode), W25Q128JV */ : #define WINBOND_NEX_W25Q256_V 0x4019 /* W25Q256FV or W25Q256JV_Q (QE=1) */ : #define WINBOND_NEX_W25Q512JV 0x4020 /* W25Q512JV */ : #define WINBOND_NEX_W25Q20_W 0x5012 /* W25Q20BW */ : #define WINBOND_NEX_W25Q40BW 0x5013 /* W25Q40BW */ : #define WINBOND_NEX_W25Q80BW 0x5014 /* W25Q80BW */ : #define WINBOND_NEX_W25Q40EW 0x6013 /* W25Q40EW */ : #define WINBOND_NEX_W25Q80EW 0x6014 /* W25Q80EW */ : #define WINBOND_NEX_W25Q16_W 0x6015 /* W25Q16DW */ : #define WINBOND_NEX_W25Q32_W 0x6016 /* W25Q32DW; W25Q32FV in QPI mode */ : #define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */ : #define WINBOND_NEX_W25Q128_W 0x6018 /* Same as W25Q128FV (QPI mode), W25R128FV */ : #define WINBOND_NEX_W25Q128FW 0x6018 /* Same as W25Q128FV (QPI mode), W25R128FV */ : #define WINBOND_NEX_W25Q256_W 0x6019 /* W25Q256JW */ : #define WINBOND_NEX_W25Q128_V_M 0x7018 /* W25Q128JVSM */ : #define WINBOND_NEX_W25Q256JV_M 0x7019 /* W25Q256JV_M (QE=0) */ : #define WINBOND_NEX_W25Q32JW 0x8016 ditto.
https://review.coreboot.org/c/flashrom/+/46064/2/flashchips.c File flashchips.c:
https://review.coreboot.org/c/flashrom/+/46064/2/flashchips.c@17197 PS2, Line 17197: .name = "W25Q32JW", : .bustype = BUS_SPI, : .manufacture_id = WINBOND_NEX_ID, : .model_id = WINBOND_NEX_W25Q32JW, : .total_size = 4096, : .page_size = 256, : .feature_bits = FEATURE_WRSR_WREN, : .tested = TEST_OK_PREW, : .probe = probe_spi_rdid, : .probe_timing = TIMING_ZERO, : .block_erasers = : { : { : .eraseblocks = { {4 * 1024, 1024} }, : .block_erase = spi_block_erase_20, : }, { : .eraseblocks = { {32 * 1024, 128} }, : .block_erase = spi_block_erase_52, : }, { : .eraseblocks = { {64 * 1024, 64} }, : .block_erase = spi_block_erase_d8, : }, { : .eraseblocks = { {4 * 1024 * 1024, 1} }, : .block_erase = spi_block_erase_60, : }, { : .eraseblocks = { {4 * 1024 * 1024, 1} }, : .block_erase = spi_block_erase_c7, : } : }, : .unlock = spi_disable_blockprotect, : .write = spi_chip_write_256, : .read = spi_chip_read, : .voltage = {1700, 1950}, : }, : : { : .vendor = "Winbond", non-spansion related, separate out.
Hello build bot (Jenkins), Edward O'Callaghan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/46064
to look at the new patch set (#3).
Change subject: flashchips.c: import chips from cros flashrom ......................................................................
flashchips.c: import chips from cros flashrom
Signed-off-by: Nikolai Artemiev nartemiev@google.com Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 --- M flashchips.c M flashchips.h 2 files changed, 236 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/46064/3
Hello build bot (Jenkins), Edward O'Callaghan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/46064
to look at the new patch set (#4).
Change subject: flashchips.c: import Spansion chips from cros flashrom ......................................................................
flashchips.c: import Spansion chips from cros flashrom
Signed-off-by: Nikolai Artemiev nartemiev@google.com Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 --- M flashchips.c M flashchips.h 2 files changed, 189 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/46064/4
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/46064 )
Change subject: flashchips.c: import Spansion chips from cros flashrom ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/flashrom/+/46064/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/flashrom/+/46064/4//COMMIT_MSG@7 PS4, Line 7: flashchips.c: import Spansion chips from cros flashrom again, details.. upstream isn't interested it was imported from cros. Only the justification on why it makes sense for upstream and details helps explain why the coding is getting added.
BUG/TEST lines are missing.
Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/46064
to look at the new patch set (#5).
Change subject: flashchips.c: add Spansion chips ......................................................................
flashchips.c: add Spansion chips
Adds support for the following chips: - S25FL128S - S25FL129P - S25FL256S - S25FS128S - {F,S,V}29C51001B
Chips imported from cros flashrom at `9c4c9a56b6a0370b383df9c75d71b3bd469e672d`.
Signed-off-by: Nikolai Artemiev nartemiev@google.com Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 --- M flashchips.c M flashchips.h 2 files changed, 189 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/46064/5
Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/46064
to look at the new patch set (#6).
Change subject: flashchips.c: add Spansion chips ......................................................................
flashchips.c: add Spansion chips
Adds support for the following chips: - S25FL128S - S25FL129P - S25FL256S - S25FS128S - {F,S,V}29C51001B
Chips imported from cros flashrom at `9c4c9a56b6a0370b383df9c75d71b3bd469e672d`.
BUG=b:153800073 TEST=builds
Signed-off-by: Nikolai Artemiev nartemiev@google.com Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 --- M flashchips.c M flashchips.h 2 files changed, 189 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/46064/6
Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/46064 )
Change subject: flashchips.c: add Spansion chips ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/flashrom/+/46064/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/flashrom/+/46064/4//COMMIT_MSG@7 PS4, Line 7: flashchips.c: import Spansion chips from cros flashrom
again, details.. upstream isn't interested it was imported from cros. […]
Done
https://review.coreboot.org/c/flashrom/+/46064/2/flashchips.h File flashchips.h:
https://review.coreboot.org/c/flashrom/+/46064/2/flashchips.h@945 PS2, Line 945: /* : * W25Q128 has several variants. Currently all are 3.3V except for the W25Q128FW : * which is 1.8V. Otherwise they should behave the same... : */ : #define WINBOND_NEX_W25Q128_V 0x4018 /* W25Q128BV, W25Q128FV (SPI mode), W25Q128JV */ : #define WINBOND_NEX_W25Q256_V 0x4019 /* W25Q256FV or W25Q256JV_Q (QE=1) */ : #define WINBOND_NEX_W25Q512JV 0x4020 /* W25Q512JV */ : #define WINBOND_NEX_W25Q20_W 0x5012 /* W25Q20BW */ : #define WINBOND_NEX_W25Q40BW 0x5013 /* W25Q40BW */ : #define WINBOND_NEX_W25Q80BW 0x5014 /* W25Q80BW */ : #define WINBOND_NEX_W25Q40EW 0x6013 /* W25Q40EW */ : #define WINBOND_NEX_W25Q80EW 0x6014 /* W25Q80EW */ : #define WINBOND_NEX_W25Q16_W 0x6015 /* W25Q16DW */ : #define WINBOND_NEX_W25Q32_W 0x6016 /* W25Q32DW; W25Q32FV in QPI mode */ : #define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */ : #define WINBOND_NEX_W25Q128_W 0x6018 /* Same as W25Q128FV (QPI mode), W25R128FV */ : #define WINBOND_NEX_W25Q128FW 0x6018 /* Same as W25Q128FV (QPI mode), W25R128FV */ : #define WINBOND_NEX_W25Q256_W 0x6019 /* W25Q256JW */ : #define WINBOND_NEX_W25Q128_V_M 0x7018 /* W25Q128JVSM */ : #define WINBOND_NEX_W25Q256JV_M 0x7019 /* W25Q256JV_M (QE=0) */ : #define WINBOND_NEX_W25Q32JW 0x8016
ditto.
Done
https://review.coreboot.org/c/flashrom/+/46064/2/flashchips.c File flashchips.c:
https://review.coreboot.org/c/flashrom/+/46064/2/flashchips.c@17197 PS2, Line 17197: .name = "W25Q32JW", : .bustype = BUS_SPI, : .manufacture_id = WINBOND_NEX_ID, : .model_id = WINBOND_NEX_W25Q32JW, : .total_size = 4096, : .page_size = 256, : .feature_bits = FEATURE_WRSR_WREN, : .tested = TEST_OK_PREW, : .probe = probe_spi_rdid, : .probe_timing = TIMING_ZERO, : .block_erasers = : { : { : .eraseblocks = { {4 * 1024, 1024} }, : .block_erase = spi_block_erase_20, : }, { : .eraseblocks = { {32 * 1024, 128} }, : .block_erase = spi_block_erase_52, : }, { : .eraseblocks = { {64 * 1024, 64} }, : .block_erase = spi_block_erase_d8, : }, { : .eraseblocks = { {4 * 1024 * 1024, 1} }, : .block_erase = spi_block_erase_60, : }, { : .eraseblocks = { {4 * 1024 * 1024, 1} }, : .block_erase = spi_block_erase_c7, : } : }, : .unlock = spi_disable_blockprotect, : .write = spi_chip_write_256, : .read = spi_chip_read, : .voltage = {1700, 1950}, : }, : : { : .vendor = "Winbond",
non-spansion related, separate out.
Done
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/46064 )
Change subject: flashchips.c: add Spansion chips ......................................................................
Patch Set 6: Code-Review+2
Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/46064
to look at the new patch set (#7).
Change subject: flashchips.c: import Spansion chips from cros flashrom ......................................................................
flashchips.c: import Spansion chips from cros flashrom
Signed-off-by: Nikolai Artemiev nartemiev@google.com Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 --- M flashchips.c M flashchips.h 2 files changed, 189 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/46064/7
Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/46064
to look at the new patch set (#8).
Change subject: flashchips.c: add Spansion chips ......................................................................
flashchips.c: add Spansion chips
Adds support for the following chips: - S25FL128S - S25FL129P - S25FL256S - S25FS128S - {F,S,V}29C51001B
Chips imported from cros flashrom at `9c4c9a56b6a0370b383df9c75d71b3bd469e672d`.
BUG=b:153800073 TEST=builds
Signed-off-by: Nikolai Artemiev nartemiev@google.com Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 --- M flashchips.c M flashchips.h 2 files changed, 189 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/46064/8
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/46064 )
Change subject: flashchips.c: add Spansion chips ......................................................................
Patch Set 8: Code-Review+2
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/46064 )
Change subject: flashchips.c: add Spansion chips ......................................................................
flashchips.c: add Spansion chips
Adds support for the following chips: - S25FL128S - S25FL129P - S25FL256S - S25FS128S - {F,S,V}29C51001B
Chips imported from cros flashrom at `9c4c9a56b6a0370b383df9c75d71b3bd469e672d`.
BUG=b:153800073 TEST=builds
Signed-off-by: Nikolai Artemiev nartemiev@google.com Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 Reviewed-on: https://review.coreboot.org/c/flashrom/+/46064 Reviewed-by: Edward O'Callaghan quasisec@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M flashchips.c M flashchips.h 2 files changed, 189 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved
diff --git a/flashchips.c b/flashchips.c index c4ba4c6..bc5de4a 100644 --- a/flashchips.c +++ b/flashchips.c @@ -16124,6 +16124,68 @@
{ .vendor = "Spansion", + .name = "S25FL128S_UL Uniform 128 kB Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128S_UL, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {128 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FL128S_US Uniform 64 kB Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128S_US, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", .name = "S25FL129P......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, @@ -16348,6 +16410,62 @@
{ .vendor = "Spansion", + .name = "S25FL256S Large Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL256S_UL, + .total_size = 16384, /* This is just half the size.... */ + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {256 * 1024, 64} }, + .block_erase = s25fl_block_erase, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FL256S Small Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL256S_US, + .total_size = 16384, /* This is just half the size.... */ + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fl_block_erase, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", .name = "S25FL256S......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, @@ -16426,6 +16544,68 @@ },
{ + .vendor = "Spansion", + .name = "S25FS128S Large Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FS128S_L, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fs_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FS128S Small Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FS128S_S, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fs_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { .vendor = "SyncMOS/MoselVitelic", .name = "{F,S,V}29C51001B", .bustype = BUS_PARALLEL, diff --git a/flashchips.h b/flashchips.h index e9c0432..394eb30 100644 --- a/flashchips.h +++ b/flashchips.h @@ -662,8 +662,17 @@ #define SPANSION_S25FL204 0x4013 #define SPANSION_S25FL208 0x4014 #define SPANSION_S25FL216 0x4015 /* Same as S25FL216K, but the latter supports OTP, 3 status regs, quad I/O, SFDP etc. */ +#define SPANSION_S25FL116K 0x4015 #define SPANSION_S25FL132K 0x4016 #define SPANSION_S25FL164K 0x4017 +#define SPANSION_S25FS128S_L 0x20180081 /* Large sectors. */ +#define SPANSION_S25FS128S_S 0x20180181 /* Small sectors. */ +#define SPANSION_S25FS256S_L 0x02190081 /* Large sectors. */ +#define SPANSION_S25FS256S_S 0x02190181 /* Small sectors. */ +#define SPANSION_S25FL128S_UL 0x20180080 /* Uniform Large (128kB) sectors */ +#define SPANSION_S25FL128S_US 0x20180180 /* Uniform Small (64kB) sectors */ +#define SPANSION_S25FL256S_UL 0x02190080 /* Uniform Large (128kB) sectors */ +#define SPANSION_S25FL256S_US 0x02190180 /* Uniform Small (64kB) sectors */
/* Spansion 29GL families got a suffix indicating the process technology but share the same 3-Byte IDs. They can * however be differentiated by CFI byte 45h. Some versions exist which have special top or bottom boot sectors
-
Edward O'Callaghan (Code Review) -
Nikolai Artemiev (Code Review)