Change in flashrom[master]: chipset_enable.c: Add support for Intel C620 Series Chipset SPI Contr...
Luka Kovacic has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44162 )
Change subject: chipset_enable.c: Add support for Intel C620 Series Chipset SPI Controller ......................................................................
chipset_enable.c: Add support for Intel C620 Series Chipset SPI Controller
Support for the Intel C620 Series Chipset SPI Controller (rev 04) is added to enable SPI flash access on the following platform:
- Intel Xeon D-2187NT
Support for this controller was shortly tested on the platform above. The flash is recognized, some regions of the flash are locked.
Signed-off-by: Luka Kovacic luka.kovacic@sartura.hr Tested-by: Jakov Petrina jakov.petrina@sartura.hr Cc: Luka Perkov luka.perkov@sartura.hr Change-Id: If39d9bb1acd4029f802a44a2940dd23f66ba09b1 --- M chipset_enable.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/44162/1
diff --git a/chipset_enable.c b/chipset_enable.c index d56a547..4772a1c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2023,6 +2023,7 @@ {0x8086, 0xa153, B_S, NT, "Intel", "QM175", enable_flash_pch100}, {0x8086, 0xa154, B_S, NT, "Intel", "CM238", enable_flash_pch100}, {0x8086, 0xa155, B_S, NT, "Intel", "QMU185", enable_flash_pch100}, + {0x8086, 0xa1a4, B_S, DEP, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c0, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c1, B_S, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c2, B_S, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620},
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44162 )
Change subject: chipset_enable.c: Add support for Intel C620 Series Chipset SPI Controller ......................................................................
Patch Set 1: Code-Review+2
Luka Kovačič has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44162 )
Change subject: chipset_enable.c: Add support for Intel C620 Series Chipset SPI Controller ......................................................................
Patch Set 1:
Hi,
Can this patch be merged, or is there anything that should be improved?
Thanks, Luka
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44162 )
Change subject: chipset_enable.c: Add support for Intel C620 Series Chipset SPI Controller ......................................................................
Patch Set 1:
Patch Set 1:
Hi,
Can this patch be merged, or is there anything that should be improved?
Thanks, Luka
Sorry, I forgot about it.
Angel Pons has submitted this change. ( https://review.coreboot.org/c/flashrom/+/44162 )
Change subject: chipset_enable.c: Add support for Intel C620 Series Chipset SPI Controller ......................................................................
chipset_enable.c: Add support for Intel C620 Series Chipset SPI Controller
Support for the Intel C620 Series Chipset SPI Controller (rev 04) is added to enable SPI flash access on the following platform:
- Intel Xeon D-2187NT
Support for this controller was shortly tested on the platform above. The flash is recognized, some regions of the flash are locked.
Signed-off-by: Luka Kovacic luka.kovacic@sartura.hr Tested-by: Jakov Petrina jakov.petrina@sartura.hr Cc: Luka Perkov luka.perkov@sartura.hr Change-Id: If39d9bb1acd4029f802a44a2940dd23f66ba09b1 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44162 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/chipset_enable.c b/chipset_enable.c index d56a547..4772a1c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2023,6 +2023,7 @@ {0x8086, 0xa153, B_S, NT, "Intel", "QM175", enable_flash_pch100}, {0x8086, 0xa154, B_S, NT, "Intel", "CM238", enable_flash_pch100}, {0x8086, 0xa155, B_S, NT, "Intel", "QMU185", enable_flash_pch100}, + {0x8086, 0xa1a4, B_S, DEP, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c0, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c1, B_S, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c2, B_S, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620},
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Angel Pons (Code Review) -
Luka Kovacic (Code Review)
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Luka Kovačič (Code Review)