Attention is currently required from: David Bartley, Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54968 )
Change subject: flashchips: add support for Winbond W25Q01JV ......................................................................
Patch Set 1:
(6 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/54968/comment/e9563905_4d8bc47c PS1, Line 17745: W25Q501V Flash chip entries are sorted alphabetically by vendor and name. This one should be placed between `W25P80` and `W25Q128.V`.
https://review.coreboot.org/c/flashrom/+/54968/comment/df90eb13_fb1880d9 PS1, Line 17745: 5 The `5` seems spurious?
https://review.coreboot.org/c/flashrom/+/54968/comment/c8b5bb4b_ce6abeb1 PS1, Line 17757: /* Full chip erase is fastest, typically takes 200s */ Block erasers for the other flash chip entries are intentionally sorted in ascending block size. Please keep this ordering.
# Context
When writing, flashrom first reads the old flash chip contents and only erases/writes the blocks which have changed. This significantly reduces flashing time when only a part of the data needs to be rewritten. This behavior is also useful when using a layout file to only rewrite specific sections of the flash chip.
However, flashrom currently always uses the first block eraser, and only falls back to the other block erasers if there's an error. Dynamically choosing the best block erasers for each case would be great to have, but someone needs to implement it. Patches are welcome!
https://review.coreboot.org/c/flashrom/+/54968/comment/9aa66627_05ce4e8c PS1, Line 17781: spi_prettyprint_status_register_plain spi_prettyprint_status_register_bp3_srwd
https://review.coreboot.org/c/flashrom/+/54968/comment/bf58c60a_28a6a207 PS1, Line 17782: spi_disable_blockprotect spi_disable_blockprotect_bp3_srwd
https://review.coreboot.org/c/flashrom/+/54968/comment/f6300f56_5c9ea10b PS1, Line 17788: nit: use only one blank line (there's two right now)
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Angel Pons (Code Review)