Attention is currently required from: Xiang W, Edward O'Callaghan, Angel Pons.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49255 )
Change subject: bitbang-spi.c: support clock polarity and phase
......................................................................
Patch Set 26:
(1 comment)
File bitbang_spi.c:
https://review.coreboot.org/c/flashrom/+/49255/comment/93f32fe3_53aa1fb6
PS26, Line 121: programmer_delay(master->half_period);
: bitbang_spi_set_sck_set_mosi(master, !cpol, (val >> i) & 1);
: programmer_delay(master->half_period);
: bitbang_spi_set_sck(master, cpol);
This does not look right and is probably what led to the follow up commit.
With cpha=0, the receiver is supposed to sample the data at the first edge.
So the sequence should be:
* set mosi
* delay
* first edge
* delay
* second edge
* (followed without delay by the next mosi setting)
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