Attention is currently required from: Nico Huber, Nikolai Artemiev, Anastasia Klimchuk. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59075 )
Change subject: [RFC][WPTST] tests: test write protection ......................................................................
Patch Set 14:
(3 comments)
Patchset:
PS13:
You need to explain what have you done in the latest patchset :) I was looking into diffs between PS […]
All changes are side-effects of rebasing onto latest WP patches which now don't support "power cycle" and "permanent" kinds of write protection.
File tests/chip_wp.c:
https://review.coreboot.org/c/flashrom/+/59075/comment/798f0c1b_2b064363 PS13, Line 260: 1
This is probably because I removed support for setting power cycle / permanent protection in a recen […]
Yes, I just adjusted tests to account for changes in WP implementation.
https://review.coreboot.org/c/flashrom/+/59075/comment/dd553d44_bfd47639 PS13, Line 390: /* Protect first 4 KiB. */
The comment has changed to opposite meaning, but range remains the same? Maybe I am missing somethin […]
Thanks, I forgot to update values to match what actually happens. The two ranges are complements of one another and CMP bit is not set here, that's why tests pass either way. The reason CMP isn't set is that it resides in SR2 which is written after SR1 and by that time WP is active and SR2 can't be changed due to hwwp=yes. This is a side-effect of having to specify state of WP pin before configuring WP.
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Sergii Dmytruk (Code Review)