[M] Change in flashrom[main]: flashchips: Add support for MXIC MX25U25645G

[DZ (Code Review)]

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer.

DZ has posted comments on this change by DZ. ( https://review.coreboot.org/c/flashrom/+/82777?usp=email )

Change subject: flashchips: Add support for MXIC MX25U25645G
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Patch Set 1:

(3 comments)

File flashchips.c:

https://review.coreboot.org/c/flashrom/+/82777/comment/33955534_cb946108?usp... :
PS1, Line 11104: 512B
> Datasheet says `8K-bit secured OTP` so I think this is 1024B

Done

https://review.coreboot.org/c/flashrom/+/82777/comment/0ef98192_3c43b37f?usp... :
PS1, Line 11111: {
               : 				.eraseblocks = { {4 * 1024, 8192} },
               : 				.block_erase = SPI_BLOCK_ERASE_21,
               : 			},
> I don't see it in datasheet (I mean: 21h, 5Ch, DCh)? I see there is: […]

Please refer to the figure-55 to figure-57 which describe 21h, 5Ch, DCh command, thanks.

https://review.coreboot.org/c/flashrom/+/82777/comment/f86d2919_27e4670d?usp... :
PS1, Line 11137: /* TODO: security register */
> You can remove TODO, you added security register bits below

Done