Nico Huber has posted comments on this change. ( https://review.coreboot.org/25047 )
Change subject: Add support for Atmel / Adesto AT25SF041 SPI flash chip ......................................................................
Patch Set 4:
(3 comments)
Before I continue the review: Is this really the version you tested? You said something about a copy of AT25DF041A on IRC, but this looks like a copy of AT26DF041 which doesn't seem to make much sense.
https://review.coreboot.org/#/c/25047/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/25047/4//COMMIT_MSG@9 PS4, Line 9: Reasonably certain this is working due to erase/read/write hardware-tests in a setup in which the flash content contained a running FPGA program. Meaningful content was stored on the chip beforehand. I read a.rom, erased, observed the FPGA dead, read b.rom, wrote back a.rom, observed the FPGA alive again. I verified b.rom in a hex editor contained 0xff only. : The FPGA data used only a small portion of the address space, so I also wrote out a file with specific 3 bytes in the first and last memory page. All flashrom verify cycles passed. Line length limit is 72 chars. I also don't see a reason for the whole story. Just stating that probe/read/erase/write was tested should be enough.
https://review.coreboot.org/#/c/25047/4/flashchips.c File flashchips.c:
https://review.coreboot.org/#/c/25047/4/flashchips.c@2194 PS4, Line 2194: .block_erase = spi_block_erase_81, Can't find anything about it in the datasheet.
https://review.coreboot.org/#/c/25047/4/flashchips.c@2197 PS4, Line 2197: .block_erase = spi_block_erase_50, 0x50 is EWSR (enable write status register)
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Nico Huber (Code Review)