Change in flashrom[master]: flashchips.c: add writeprotect support for more chips

[Nikolai Artemiev (Code Review)]

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk.
Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62214 )

Change subject: flashchips.c: add writeprotect support for more chips
......................................................................

Patch Set 26:

(1 comment)

Commit Message:

https://review.coreboot.org/c/flashrom/+/62214/comment/2706778b_f4f909b7 
PS26, Line 10:  Chips I wasn't able to test were just
             : checked against the datasheets.
> Could a EM100 be leveraged here?

I just tried it, it would have been a great way to test but it appears that SR2 commands are being intrepreted incorrectly, e.g.

0x35 should be read sr2 and 0x31 should be write sr2.

```
em100 -c GD25Q64 --stop -t --start`
...
0x35 - enter quad I/O mode
...
0x31 - unknown command
```