Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk.

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1 comment:

• Commit Message:

  • Patch Set #26, Line 10:

     Chips I wasn't able to test were just
    checked against the datasheets.
    

    Could a EM100 be leveraged here?

    I just tried it, it would have been a great way to test but it appears that SR2 commands are being intrepreted incorrectly, e.g.

    0x35 should be read sr2 and 0x31 should be write sr2.

    ```
    em100 -c GD25Q64 --stop -t --start`
    ...
    0x35 - enter quad I/O mode
    ...
    0x31 - unknown command
    ```

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