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[M] Change in flashrom[main]: flashchips: add GD25B512MF and GD25R512MF
by Anastasia Klimchuk (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/84083?usp=email ) Change subject: flashchips: add GD25B512MF and GD25R512MF ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > All good in the code, but you will need to rebase this patch on the top of main branch. […] I rebased the patch -- To view, visit https://review.coreboot.org/c/flashrom/+/84083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Gerrit-Change-Number: 84083 Gerrit-PatchSet: 3 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 08:28:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: flashchips: add GD25B512MF and GD25R512MF
by Anastasia Klimchuk (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has uploaded a new patch set (#3) to the change originally created by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/84083?usp=email ) Change subject: flashchips: add GD25B512MF and GD25R512MF ...................................................................... flashchips: add GD25B512MF and GD25R512MF GD25B512MF: 3V 512Mbit, QE = 1 GD25R512MF: GD25B512MF feature + RPMC These two part share the same datasheet on the flash side. https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240412/DS-0… Tested both models on ch347 with erase, write, read, and protection. Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- M flashchips.c M include/flashchips.h 2 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/84083/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/84083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Gerrit-Change-Number: 84083 Gerrit-PatchSet: 3 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com>

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[M] Change in flashrom[main]: flashchips: add GD25B512MF and GD25R512MF
by Anastasia Klimchuk (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has uploaded a new patch set (#2) to the change originally created by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/84083?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Anastasia Klimchuk, Verified+1 by build bot (Jenkins) Change subject: flashchips: add GD25B512MF and GD25R512MF ...................................................................... flashchips: add GD25B512MF and GD25R512MF GD25B512MF: 3V 512Mbit, QE = 1 GD25R512MF: GD25B512MF feature + RPMC These two part share the same datasheet on the flash side. https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240412/DS-0… Tested both models on ch347 with erase, write, read, and protection. Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- M flashchips.c M include/flashchips.h 2 files changed, 58 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/84083/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/84083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Gerrit-Change-Number: 84083 Gerrit-PatchSet: 2 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com>

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[M] Change in flashrom[main]: ch347_spi: Add spi clock frequency selection
by Anastasia Klimchuk (Code Review) 29 Aug '24

29 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email ) Change subject: ch347_spi: Add spi clock frequency selection ...................................................................... ch347_spi: Add spi clock frequency selection CH347 SPI interface supports up to 60M. For example, to set a 30M spi rate, use -p ch347_spi:spispeed=30M. Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Signed-off-by: ZhiYuanNJ Liu <871238103(a)qq.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82776 Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M ch347_spi.c M doc/classic_cli_manpage.rst 2 files changed, 46 insertions(+), 5 deletions(-) Approvals: Anastasia Klimchuk: Looks good to me, approved build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/ch347_spi.c b/ch347_spi.c index 21dcabb..34f2741 100644 --- a/ch347_spi.c +++ b/ch347_spi.c @@ -51,6 +51,11 @@ int interface; }; +struct device_speeds { + const char *name; + const int divisor; +}; + /* TODO: Add support for HID mode */ static const struct dev_entry devs_ch347_spi[] = { {0x1A86, 0x55DB, OK, "QinHeng Electronics", "USB To UART+SPI+I2C"}, /* CH347T */ @@ -63,6 +68,18 @@ CH347F_IFACE, }; +static const struct device_speeds spispeeds[] = { + {"60M", 0}, + {"30M", 1}, + {"15M", 2}, + {"7.5M", 3}, + {"3.75M", 4}, + {"1.875M", 5}, + {"937.5K", 6}, + {"468.75K", 7}, + {NULL, 0} +}; + static int ch347_spi_shutdown(void *data) { struct ch347_spi_data *ch347_data = data; @@ -266,9 +283,11 @@ /* Largely copied from ch341a_spi.c */ static int ch347_spi_init(const struct programmer_cfg *cfg) { + char *arg; uint16_t vid = devs_ch347_spi[0].vendor_id; uint16_t pid = 0; int index = 0; + int speed_index = 2; struct ch347_spi_data *ch347_data = calloc(1, sizeof(*ch347_data)); if (!ch347_data) { msg_perr("Could not allocate space for SPI data\n"); @@ -332,9 +351,25 @@ (desc.bcdDevice >> 4) & 0x000F, (desc.bcdDevice >> 0) & 0x000F); - /* TODO: add programmer cfg for things like CS pin and divisor */ - if (ch347_spi_config(ch347_data, 2) < 0) + /* set CH347 clock division */ + arg = extract_programmer_param_str(cfg, "spispeed"); + if (arg) { + for (speed_index = 0; spispeeds[speed_index].name; speed_index++) { + if (!strncasecmp(spispeeds[speed_index].name, arg, strlen(spispeeds[speed_index].name))) { + break; + } + } + } + if (!spispeeds[speed_index].name || !arg) { + msg_perr("Unknown value of spispeed parameter, using default 15MHz clock spi.\n"); + speed_index = 2; + } + free(arg); + if (ch347_spi_config(ch347_data, spispeeds[speed_index].divisor) < 0) { goto error_exit; + } else { + msg_pinfo("CH347 SPI clock set to %sHz.\n", spispeeds[speed_index].name); + } return register_spi_master(&spi_master_ch347_spi, ch347_data); @@ -348,4 +383,4 @@ .type = USB, .devs.dev = devs_ch347_spi, .init = ch347_spi_init, -}; +}; \ No newline at end of file diff --git a/doc/classic_cli_manpage.rst b/doc/classic_cli_manpage.rst index 932f4c9..e2ce684 100644 --- a/doc/classic_cli_manpage.rst +++ b/doc/classic_cli_manpage.rst @@ -1035,8 +1035,14 @@ ch347_spi programmer ^^^^^^^^^^^^^^^^^^^^ -The WCH CH347 programmer does not currently support any parameters. SPI frequency is fixed at 2 MHz, and CS0 is used -as per the device. +An optional ``spispeed`` parameter could be used to specify the SPI speed. This parameter is available for the CH347T and CH347F device. +The default SPI speed is 15MHz if no value is specified. +Syntax is:: + + flashrom -p ch347_spi:spispeed=value + +where ``value`` can be ``60M``, ``30M``, ``15M``, ``7.5M``, ``3.75M``, ``1.875M``, ``937.5K``, ``468.75K``. + ni845x_spi programmer ^^^^^^^^^^^^^^^^^^^^^ -- To view, visit https://review.coreboot.org/c/flashrom/+/82776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Gerrit-Change-Number: 82776 Gerrit-PatchSet: 15 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: flashchips: add GD25B512MF and GD25R512MF
by Anastasia Klimchuk (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/84083?usp=email ) Change subject: flashchips: add GD25B512MF and GD25R512MF ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: All good in the code, but you will need to rebase this patch on the top of main branch. It says "merge conflict", but I think there is no actual conflict. It's just that the adjacent lines, just before in the same file, were submitted in the other patch earlier. Tell me if rebasing won't work, I will have a look. -- To view, visit https://review.coreboot.org/c/flashrom/+/84083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Gerrit-Change-Number: 84083 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 02:44:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in flashrom[main]: reduce DELAY_MINIMUM_SLEEP_US to 100 by default
by Anastasia Klimchuk (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Peter Marheine, Thomas Heijligen. Anastasia Klimchuk has posted comments on this change by Peter Marheine. ( https://review.coreboot.org/c/flashrom/+/81608?usp=email ) Change subject: reduce DELAY_MINIMUM_SLEEP_US to 100 by default ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/81608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0f431d240c670446218b14811ef62a34e4c83da2 Gerrit-Change-Number: 81608 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Thu, 29 Aug 2024 02:19:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in flashrom[main]: reduce DELAY_MINIMUM_SLEEP_US to 100 by default
by Peter Marheine (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Anastasia Klimchuk, Thomas Heijligen. Peter Marheine has posted comments on this change by Peter Marheine. ( https://review.coreboot.org/c/flashrom/+/81608?usp=email ) Change subject: reduce DELAY_MINIMUM_SLEEP_US to 100 by default ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Rebased since we no longer have a Makefile. I think this is good to go now. -- To view, visit https://review.coreboot.org/c/flashrom/+/81608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0f431d240c670446218b14811ef62a34e4c83da2 Gerrit-Change-Number: 81608 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 29 Aug 2024 00:02:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in flashrom[main]: reduce DELAY_MINIMUM_SLEEP_US to 100 by default
by Peter Marheine (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Anastasia Klimchuk, Thomas Heijligen. Hello Anastasia Klimchuk, Thomas Heijligen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/81608?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: reduce DELAY_MINIMUM_SLEEP_US to 100 by default ...................................................................... reduce DELAY_MINIMUM_SLEEP_US to 100 by default This makes flashrom sleep more eagerly rather than busy-waiting, observing that most delays in flashrom are either less than 100 microseconds (barely enough time to get any work done, even on a fast machine) or much more than 1 millisecond (very wasteful to busy-loop). Since we believe most systems offer good timer resolution that should provide sleep latency on the order of 100 microseconds, this is a reasonable default. For DOS, the default is set to 50ms because the best available timing source on DOS only ticks at about 20 Hz. Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> Change-Id: I0f431d240c670446218b14811ef62a34e4c83da2 --- M meson_cross/i586_djgpp_dos.txt M meson_options.txt 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/81608/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/81608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0f431d240c670446218b14811ef62a34e4c83da2 Gerrit-Change-Number: 81608 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: flashchips: redo add GD25B256E and GD25R256E
by Anastasia Klimchuk (Code Review) 27 Aug '24

27 Aug '24

Anastasia Klimchuk has abandoned this change. ( https://review.coreboot.org/c/flashrom/+/84082?usp=email ) Change subject: flashchips: redo add GD25B256E and GD25R256E ...................................................................... Abandoned Submitted in CB:83998 -- To view, visit https://review.coreboot.org/c/flashrom/+/84082?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I1596628211d508d3057893c049f1a1c95a123073 Gerrit-Change-Number: 84082 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: flashchips: add GD25B256E and GD25R256E
by Anastasia Klimchuk (Code Review) 27 Aug '24

27 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83998?usp=email ) Change subject: flashchips: add GD25B256E and GD25R256E ...................................................................... flashchips: add GD25B256E and GD25R256E removed FEATURE_WRSR_EXT2 from the model after datasheet review. replace printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, .unlock = SPI_DISABLE_BLOCKPROTECT, with .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, GD25B256E: 3V 256Mbit, Quad enabled. GD25R256E: GD25B256E features + RPMC, so they share the same datasheet on flash side https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-0… Tested both models on ch347 with erase, write, read and protection. Change-Id: Ie733e0c2e35fa4797f5198f2c8334469b65f402c Signed-off-by: Victor Lim <vlim(a)gigadevice.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83998 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c M include/flashchips.h 2 files changed, 6 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 40a3f2b..0c8517f 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7583,14 +7583,13 @@ { .vendor = "GigaDevice", - .name = "GD25Q256D/GD25Q256E", + .name = "GD25Q256E/GD25B256E/GD25R256E/GD25Q256D", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q256D, .total_size = 32768, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | - FEATURE_WRSR_EXT2 | FEATURE_WRSR2 | FEATURE_WRSR3, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2 | FEATURE_WRSR3, .tested = TEST_OK_PREWB, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, @@ -7622,8 +7621,8 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, - .unlock = SPI_DISABLE_BLOCKPROTECT, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, .voltage = {2700, 3600}, @@ -7632,7 +7631,7 @@ .srp = {STATUS1, 7, RW}, .srl = {STATUS2, 6, RW}, .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, - .tb = {STATUS1, 6, RW}, + .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */ }, .decode_range = DECODE_RANGE_SPI25, }, diff --git a/include/flashchips.h b/include/flashchips.h index 02de72a..4456587 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -395,7 +395,7 @@ #define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */ #define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */ #define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C,and GD25Q128E, GD25B128E, GD25R128E can be distinguished by SFDP */ -#define GIGADEVICE_GD25Q256D 0x4019 +#define GIGADEVICE_GD25Q256D 0x4019 /* Same as GD25B256E, GD25Q256E, GD25R256E */ #define GIGADEVICE_GD25VQ21B 0x4212 #define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */ #define GIGADEVICE_GD25VQ80C 0x4214 -- To view, visit https://review.coreboot.org/c/flashrom/+/83998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie733e0c2e35fa4797f5198f2c8334469b65f402c Gerrit-Change-Number: 83998 Gerrit-PatchSet: 5 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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