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[S] Change in flashrom[main]: [WIP] Fix FEATURE_NO_ERASE chips and add test for them
by Anastasia Klimchuk (Code Review) 04 Sep '24

04 Sep '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/84203?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: [WIP] Fix FEATURE_NO_ERASE chips and add test for them ...................................................................... [WIP] Fix FEATURE_NO_ERASE chips and add test for them Change-Id: I582fe00da0715e9b5e92fcc9d15d5a90a2615117 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M flashrom.c M tests/chip.c M tests/tests.c M tests/tests.h 4 files changed, 46 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/84203/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/84203?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I582fe00da0715e9b5e92fcc9d15d5a90a2615117 Gerrit-Change-Number: 84203 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: [WIP] Fix FEATURE_NO_ERASE chips and add test for them
by Anastasia Klimchuk (Code Review) 04 Sep '24

04 Sep '24

Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/84203?usp=email ) Change subject: [WIP] Fix FEATURE_NO_ERASE chips and add test for them ...................................................................... Patch Set 1: (1 comment) File tests/chip.c: https://review.coreboot.org/c/flashrom/+/84203/comment/cb5fb75d_d3703c7c?us… : PS1, Line 418: 0xCC If this value changed to 0xAC (something different from initial content), the test times out. Needs investigation -- To view, visit https://review.coreboot.org/c/flashrom/+/84203?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I582fe00da0715e9b5e92fcc9d15d5a90a2615117 Gerrit-Change-Number: 84203 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Wed, 04 Sep 2024 03:30:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in flashrom[main]: [WIP] Fix FEATURE_NO_ERASE chips and add test for them
by Anastasia Klimchuk (Code Review) 04 Sep '24

04 Sep '24

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/84203?usp=email ) Change subject: [WIP] Fix FEATURE_NO_ERASE chips and add test for them ...................................................................... [WIP] Fix FEATURE_NO_ERASE chips and add test for them Change-Id: I582fe00da0715e9b5e92fcc9d15d5a90a2615117 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M flashrom.c M tests/chip.c M tests/tests.c M tests/tests.h 4 files changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/84203/1 diff --git a/flashrom.c b/flashrom.c index 01a41c4..5dee1fc 100644 --- a/flashrom.c +++ b/flashrom.c @@ -482,7 +482,7 @@ return 1; } - if (flash->mst->buses_supported & BUS_SPI) { + if (!(flash->chip->feature_bits & FEATURE_NO_ERASE) && flash->mst->buses_supported & BUS_SPI) { const uint8_t *opcode = spi_get_opcode_from_erasefn(eraser.block_erase); for (int i = 0; opcode[i]; i++) { if (!spi_probe_opcode(flash, opcode[i])) { diff --git a/tests/chip.c b/tests/chip.c index 3e1ae3b..9e87d30 100644 --- a/tests/chip.c +++ b/tests/chip.c @@ -132,6 +132,22 @@ }}, }; +static const struct flashchip chip_no_erase = { + .vendor = "aklm", + .bustype = BUS_SPI, + .total_size = MOCK_CHIP_SIZE / KiB, + .tested = TEST_OK_PREW, + .read = TEST_READ_INJECTOR, + .write = TEST_WRITE_INJECTOR, + .page_size = 256, + .feature_bits = FEATURE_NO_ERASE | FEATURE_ERASED_ZERO, + .block_erasers = + {{ + .eraseblocks = { {MOCK_CHIP_SIZE, 1} }, + .block_erase = SPI_BLOCK_ERASE_EMULATION, + }}, +}; + /* Setup the struct for W25Q128.V, all values come from flashchips.c */ static const struct flashchip chip_W25Q128_V = { .vendor = "aklm&dummyflasher", @@ -384,6 +400,32 @@ free(newcontents); } +void write_chip_feature_no_erase(void **state) +{ + (void) state; /* unused */ + + g_test_write_injector = write_chip; + g_test_read_injector = read_chip; + struct flashrom_flashctx flashctx = { 0 }; + struct flashrom_layout *layout; + struct flashchip mock_chip = chip_no_erase; + const char *param = "bus=spi"; + + setup_chip(&flashctx, &layout, &mock_chip, param, NULL); + + uint8_t *const newcontents = malloc(MOCK_CHIP_SIZE); + assert_non_null(newcontents); + memset(newcontents, 0xCC, MOCK_CHIP_SIZE); + + printf("Write chip operation started.\n"); + assert_int_equal(0, flashrom_image_write(&flashctx, newcontents, MOCK_CHIP_SIZE, NULL)); + assert_int_equal(0, flashrom_image_verify(&flashctx, newcontents, MOCK_CHIP_SIZE)); + printf("Write chip operation done.\n"); + + teardown(&layout); + + free(newcontents); +} void write_nonaligned_region_with_dummyflasher_test_success(void **state) { (void) state; /* unused */ diff --git a/tests/tests.c b/tests/tests.c index 165390a..78f1b47 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -498,6 +498,7 @@ cmocka_unit_test(read_chip_with_dummyflasher_test_success), cmocka_unit_test(write_chip_test_success), cmocka_unit_test(write_chip_with_dummyflasher_test_success), + cmocka_unit_test(write_chip_feature_no_erase), cmocka_unit_test(write_nonaligned_region_with_dummyflasher_test_success), cmocka_unit_test(verify_chip_test_success), cmocka_unit_test(verify_chip_with_dummyflasher_test_success), diff --git a/tests/tests.h b/tests/tests.h index 8cf8be0..3536d1d 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -86,6 +86,7 @@ void read_chip_with_dummyflasher_test_success(void **state); void write_chip_test_success(void **state); void write_chip_with_dummyflasher_test_success(void **state); +void write_chip_feature_no_erase(void **state); void write_nonaligned_region_with_dummyflasher_test_success(void **state); void verify_chip_test_success(void **state); void verify_chip_with_dummyflasher_test_success(void **state); -- To view, visit https://review.coreboot.org/c/flashrom/+/84203?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I582fe00da0715e9b5e92fcc9d15d5a90a2615117 Gerrit-Change-Number: 84203 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>

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[XS] Change in flashrom[main]: reduce DELAY_MINIMUM_SLEEP_US to 100 by default
by Peter Marheine (Code Review) 02 Sep '24

02 Sep '24

Peter Marheine has submitted this change. ( https://review.coreboot.org/c/flashrom/+/81608?usp=email ) Change subject: reduce DELAY_MINIMUM_SLEEP_US to 100 by default ...................................................................... reduce DELAY_MINIMUM_SLEEP_US to 100 by default This makes flashrom sleep more eagerly rather than busy-waiting, observing that most delays in flashrom are either less than 100 microseconds (barely enough time to get any work done, even on a fast machine) or much more than 1 millisecond (very wasteful to busy-loop). Since we believe most systems offer good timer resolution that should provide sleep latency on the order of 100 microseconds, this is a reasonable default. For DOS, the default is set to 50ms because the best available timing source on DOS only ticks at about 20 Hz. Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> Change-Id: I0f431d240c670446218b14811ef62a34e4c83da2 Reviewed-on: https://review.coreboot.org/c/flashrom/+/81608 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M meson_cross/i586_djgpp_dos.txt M meson_options.txt 2 files changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/meson_cross/i586_djgpp_dos.txt b/meson_cross/i586_djgpp_dos.txt index 3d97aab..a1f2401 100644 --- a/meson_cross/i586_djgpp_dos.txt +++ b/meson_cross/i586_djgpp_dos.txt @@ -30,6 +30,8 @@ [project options] tests = 'disabled' ich_descriptors_tool = 'disabled' +# DOS time resolution is only about 50ms +delay_minimum_sleep_us = 50000 [properties] sys_root = '/usr/local/djgpp' diff --git a/meson_options.txt b/meson_options.txt index 0f56e26..6df95ba 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -21,6 +21,6 @@ option('documentation', type : 'feature', value : 'auto', description : 'build the html documentation') option('ni845x_search_path', type : 'string', value : 'C:\Program Files (x86)\National Instruments\Ni-845x\MS Visual C', description : 'Path to search for the proprietary ni845x library and header (32-bit Windows only)') -option('delay_minimum_sleep_us', type : 'integer', min : 0, value : 100000, +option('delay_minimum_sleep_us', type : 'integer', min : 0, value : 100, description : 'Minimum time in microseconds to suspend execution for (rather than polling) when a delay is required.' + ' Larger values may perform better on machines with low timer resolution, at the cost of increased power.') -- To view, visit https://review.coreboot.org/c/flashrom/+/81608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0f431d240c670446218b14811ef62a34e4c83da2 Gerrit-Change-Number: 81608 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: tests: Check verify op completed in full if chip memory modified
by Anastasia Klimchuk (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Aarya, Anastasia Klimchuk, Peter Marheine. Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/84078?usp=email ) Change subject: tests: Check verify op completed in full if chip memory modified ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: There are a few changes in the new patchset: 1) Stronger requirement on verify: verify records cleared after each modification. In cases when the memory area is erased, and then written, we want to ensure verification happens after write, not just after erase. 2) FLASHROM_FLAG_VERIFY_AFTER_WRITE turned ON for all usual cases 3) FLASHROM_FLAG_VERIFY_AFTER_WRITE turned OFF for protected region test cases, verify op called manually after write. (because protected region not supposed to be modified) 4) protected region in the test changed to be only write-protected , read allowed, to be able to do verification 5) fixed a bug in post-processing of unaligned region when the end region needs to be extended. newcontents are supposed to be restored, but there was 1-off error. How do 3 and 4 work in real life? Is the test close enough to real life? Commit Message: https://review.coreboot.org/c/flashrom/+/84078/comment/e7c9094a_a0bf0fe5?us… : PS1, Line 18: Note: at the moment the test is not fully working, the following : write test cases fail (all erase test cases pass): > Looks like it might be a fencepost error (possibly treating the upper bound of a region as exclusive […] This specific error was because verify_after_write flag was off! It is turned on in cli_classic, but tests are calling libflashrom directly, so the flag needs to be explicitly turned on. The only verification that happened without the flag, was coming from after the erase operation, because erase ignores the flags :) I found a fencepost bug in the other place though! (in erasure_layout.c) -- To view, visit https://review.coreboot.org/c/flashrom/+/84078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I3c5d55a0deb20f23f4072caac8c0dce04cc98fd4 Gerrit-Change-Number: 84078 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Sep 2024 12:39:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org>

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[M] Change in flashrom[main]: tests: Check verify op completed in full if chip memory modified
by Anastasia Klimchuk (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Aarya, Peter Marheine. Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/84078?usp=email ) Change subject: tests: Check verify op completed in full if chip memory modified ...................................................................... Patch Set 2: (2 comments) File tests/erase_func_algo.c: https://review.coreboot.org/c/flashrom/+/84078/comment/e8a9b973_fbce8b31?us… : PS1, Line 60: uint8_t > Since this is true/false, just use `bool`. Done https://review.coreboot.org/c/flashrom/+/84078/comment/2c96901a_682f053a?us… : PS1, Line 77: == 0x1 > I'd rather use implicit boolean conversion throughout (`if (g_state.was_modified[start])`). Done -- To view, visit https://review.coreboot.org/c/flashrom/+/84078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I3c5d55a0deb20f23f4072caac8c0dce04cc98fd4 Gerrit-Change-Number: 84078 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Sep 2024 12:21:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org>

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[M] Change in flashrom[main]: tests: Check verify op completed in full if chip memory modified
by Anastasia Klimchuk (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Anastasia Klimchuk. Hello Peter Marheine, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/84078?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: tests: Check verify op completed in full if chip memory modified ...................................................................... tests: Check verify op completed in full if chip memory modified The patch adds new functionality to the test: tracking the areas of chip memory that were modified (i.e. by erase or write operation), and then checking those areas were completely covered by verify operation. The test operates over the mock chip memory of 16 bytes, so it is possible to track each byte which was modified, and assert that is has been verified afterwards. Adding the test found a bug which is fixed in this commit. Post-cleanup after processing unaligned region for the case when end region needs to be extended to align with erase block. Writing was done correctly, but post-processing of newcontents could go wrong, which would make verification appear false-negative. Note: at the moment the test is not fully working, test cases #19 are both failing, for the reason they are very edge cases with logical layout covering only a part of the chip, and also this layout being unaligned and smaller than the smallest erase block. Probably needs some clever hack for testing verification. [ FAILED ] 2 test(s), listed below: [ FAILED ] Erase test case #19 [ FAILED ] Write test case #19 Change-Id: I3c5d55a0deb20f23f4072caac8c0dce04cc98fd4 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M erasure_layout.c M tests/erase_func_algo.c 2 files changed, 119 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/84078/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/84078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I3c5d55a0deb20f23f4072caac8c0dce04cc98fd4 Gerrit-Change-Number: 84078 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: flashchips: add GD25F256F
by Anastasia Klimchuk (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/84090?usp=email ) Change subject: flashchips: add GD25F256F ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/84090/comment/f12ac706_6445cc8d?us… : PS1, Line 10: Will send the datasheet. Got it by email, you can remove this line, thank you! File flashchips.c: https://review.coreboot.org/c/flashrom/+/84090/comment/3540b503_f38d7516?us… : PS1, Line 8058: STATUS1, 7 But this bit (S7 on page 14) is marked as Reserved? -- To view, visit https://review.coreboot.org/c/flashrom/+/84090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ibbbbb8a55adbcbc2ee1785782c4eb3771d50c167 Gerrit-Change-Number: 84090 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 04:02:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in flashrom[main]: flashchips: add GD25B512MF and GD25R512MF
by Anastasia Klimchuk (Code Review) 01 Sep '24

01 Sep '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/84083?usp=email ) Change subject: flashchips: add GD25B512MF and GD25R512MF ...................................................................... flashchips: add GD25B512MF and GD25R512MF GD25B512MF: 3V 512Mbit, QE = 1 GD25R512MF: GD25B512MF feature + RPMC These two part share the same datasheet on the flash side. https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240412/DS-0… Tested both models on ch347 with erase, write, read, and protection. Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Signed-off-by: Victor Lim <vlim(a)gigadevice.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84083 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M flashchips.c M include/flashchips.h 2 files changed, 57 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 0c8517f..02eefa4 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7636,6 +7636,62 @@ .decode_range = DECODE_RANGE_SPI25, }, +{ + .vendor = "GigaDevice", + .name = "GD25B512MF/GD25R512MF", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25B512MF, + .total_size = 65536, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2 | FEATURE_WRSR3 | FEATURE_4BA, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_5C, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {64 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {64 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */ + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 6, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */ + .cmp = {STATUS3, 3, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + { .vendor = "GigaDevice", .name = "GD25Q32(B)", diff --git a/include/flashchips.h b/include/flashchips.h index 4456587..5f3bed0 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -396,6 +396,7 @@ #define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */ #define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C,and GD25Q128E, GD25B128E, GD25R128E can be distinguished by SFDP */ #define GIGADEVICE_GD25Q256D 0x4019 /* Same as GD25B256E, GD25Q256E, GD25R256E */ +#define GIGADEVICE_GD25B512MF 0x401A /* Same as GD25R512MF */ #define GIGADEVICE_GD25VQ21B 0x4212 #define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */ #define GIGADEVICE_GD25VQ80C 0x4214 -- To view, visit https://review.coreboot.org/c/flashrom/+/84083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Gerrit-Change-Number: 84083 Gerrit-PatchSet: 4 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: flashchips: add GD25B512MF and GD25R512MF
by Anastasia Klimchuk (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/84083?usp=email ) Change subject: flashchips: add GD25B512MF and GD25R512MF ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/84083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Gerrit-Change-Number: 84083 Gerrit-PatchSet: 3 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 10:03:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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