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Change subject: layout: Factor out flash_region structure from romentry
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
What benefit does this provide?
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Change subject: tests: ensure chip erase operation is executed
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
File include/flash.h:
https://review.coreboot.org/c/flashrom/+/69130/comment/6a0752d0_d672b9b3
PS1, Line 159: #define UNERASED_VALUE(flash)
> https://chromium.googlesource.com/chromiumos/third_party/flashrom/+/refs/he…. […]
UNERASED_VALUE could also be 0x55. If any chip ever erases to 0x55, whoever manufactured it deserves to be slapped 😄
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69129 )
Change subject: writeprotect,ichspi,spi25: handle register access constraints
......................................................................
Patch Set 5:
(1 comment)
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/69129/comment/aca35aa6_cf0878f9
PS5, Line 110: (struct flashctx *)
Isn't this casting away `const` from the data pointed by `flash`?
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Change subject: ichspi.c: Read chip ID and use it to identify chip
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/69195/comment/26bea737_a2efa6a2
PS2, Line 7: ichspi.c: Read chip ID and use it to identify chip
Knowing the chip shouldn't matter for hwseq, as we're not sending direct commands anyway.
Also, what about systems with two flash chips? Yes, they exist (Ivy Bridge and Haswell ThinkPads, for example), and flashrom always uses hwseq.
https://review.coreboot.org/c/flashrom/+/69195/comment/605ea5a4_e66693e7
PS2, Line 9: BUG=b:253715389,b:253713774
Out of curiosity, what are these bug tracker entries about?
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Change subject: flashchips: add support for MX77L25650F chip
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Patch Set 3: Code-Review+1
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/68557/comment/b280c09d_354da788
PS1, Line 10215: // TODO: add 64K block erase
> We haven't tested 64K erase so I didn't add it here.
We typically add all block erasers supported by the flash chip, from smallest block size to largest block size. flashrom currently doesn't use them unless there's an error.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67393 )
Change subject: tree/: Move programmer_delay() out of programmer state machine
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Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/67393/comment/95d790e2_f030f860
PS4, Line 13:
> Sorry for the late reply, couldn't sleep properly for more than a week... […]
Hmmm, looks like the main source of confusion is lack of documentation regarding flashrom layers and structures. Will start a thread on the mailing list asking for information.
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Change subject: programmer: Drop dead fallback_map() boilerplate
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
Needs rebase
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Change subject: sb600spi.c: Drop "Promontory" support
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Maybe we should do this on the master branch too. At the very least, the Promontory name is wrong.
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