Attention is currently required from: Thomas Heijligen.
Hello build bot (Jenkins), Thomas Heijligen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69714
to look at the new patch set (#3).
Change subject: flashrom/gui: Add GUI to Flashrom
......................................................................
flashrom/gui: Add GUI to Flashrom
Flashrom Graphical User Interface
Depends on:
* gtk+ >=4
* adwaita >=1
Shortcomings:
* Untested
TODO:
* Test on as many hardware/platforms as possible
Change-Id: I130028b07e0465a2c877d5cbbdc2edd9ea5e8266
Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com>
---
A gflashrom/Makefile
A gflashrom/chartable.c
A gflashrom/chartable.h
A gflashrom/common_macros.h
A gflashrom/common_ui.c
A gflashrom/common_ui.h
A gflashrom/config.h
A gflashrom/configuration.c
A gflashrom/configuration.h
A gflashrom/context_menu.ui.xml
A gflashrom/converter.c
A gflashrom/converter.h
A gflashrom/coreboot.Gflashrom.gschema.xml
A gflashrom/data_buffer.c
A gflashrom/data_buffer.h
A gflashrom/find_dialog.ui.xml
A gflashrom/find_options.ui.xml
A gflashrom/findreplace.c
A gflashrom/findreplace.h
A gflashrom/flashrom.c
A gflashrom/gflashrom.c
A gflashrom/gflashrom.css
A gflashrom/gflashrom.gresource.xml
A gflashrom/gflashrom.h
A gflashrom/gflashrom_app_win.c
A gflashrom/gflashrom_app_win.h
A gflashrom/gflashrom_app_win.ui.xml
A gflashrom/gflashrom_layout_manager.c
A gflashrom/gflashrom_layout_manager.h
A gflashrom/gflashrom_paste_data.c
A gflashrom/gflashrom_paste_data.h
A gflashrom/gflashrom_resources.c
A gflashrom/gfprint.c
A gflashrom/help_overlay.ui.xml
A gflashrom/hex_dialog.c
A gflashrom/hex_dialog.h
A gflashrom/hex_document.c
A gflashrom/hex_document.h
A gflashrom/hex_statusbar.c
A gflashrom/hex_statusbar.h
A gflashrom/jump_dialog.ui.xml
A gflashrom/main.c
A gflashrom/objects.c
A gflashrom/objects.h
A gflashrom/paste_special.c
A gflashrom/paste_special.h
A gflashrom/paste_special.ui.xml
A gflashrom/preferences.c
A gflashrom/preferences.h
A gflashrom/preferences.ui.xml
A gflashrom/print.c
A gflashrom/print.h
A gflashrom/replace_dialog.ui.xml
53 files changed, 17,562 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/14/69714/3
--
To view, visit https://review.coreboot.org/c/flashrom/+/69714
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I130028b07e0465a2c877d5cbbdc2edd9ea5e8266
Gerrit-Change-Number: 69714
Gerrit-PatchSet: 3
Gerrit-Owner: Iman Bingi <imanbingy(a)gmail.com>
Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Thomas Heijligen <src(a)posteo.de>
Gerrit-MessageType: newpatchset
Attention is currently required from: Edward O'Callaghan, Angel Pons, Nikolai Artemiev.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69422 )
Change subject: ichspi: clear byte count in ich_start_hwseq_xfer()
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Also thank you Angel for pulling on this thread to get a deeper investigation going here so that we could get to the bottom of this.
Missed to answer the question from Angel
> Looking at CB:62869 it did not clear the byte count before.
As per the EDS, FDBC field is don't care for any block erase operation.
--
To view, visit https://review.coreboot.org/c/flashrom/+/69422
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I2535bdfb77ff370bddcb507a229bbf4119681cdf
Gerrit-Change-Number: 69422
Gerrit-PatchSet: 2
Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com>
Gerrit-Comment-Date: Fri, 18 Nov 2022 11:29:45 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>
Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org>
Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: comment
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69789 )
Change subject: ichspi: Fix number of bytes for HW seq operations
......................................................................
ichspi: Fix number of bytes for HW seq operations
This patch fixes a potential issue where the SPI controller register
HSFC.FDBC (bits 24-29) value gets incorrectly calculated while passing
the `len` as `0` instead of `1`.
As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f`
represents 64-bytes to be transferred. The number of bytes
transferred is the value of this field plus 1.
If we would like to transfer 1 byte then we need to set `0b` in
FDBC for operations like read, write, flash id as to account for
the `set byte count` hence, the `len` argument should be `1`.
Additionally, as per EDS, the FDBC field is ignored for any block
erase command.
BUG=b:258280679
TEST=Able to build flashrom and perform below operations on Google,
Rex and Google, Kano/Taeko.
During `--wp-disable` HW seq operation that requires 1 byte data
transfer.
HSFC.FDBC value while passing `len` as `0` = 0x3f (represents 64-byte)
HSFC.FDBC value while passing `len` as `1` = 0x0 (represents 1-byte)
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I5b911655649c693e576497520687d7810bbd3c54
---
M ichspi.c
1 file changed, 45 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/89/69789/1
diff --git a/ichspi.c b/ichspi.c
index a3552d3..58b74dc 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1364,6 +1364,12 @@
hsfc = REGREAD16(ICH9_REG_HSFC);
hsfc &= ~hwseq_data->hsfc_fcycle; /* clear operation */
hsfc |= hsfc_cycle;
+ /*
+ * The number of bytes transferred is the value of `FDBC` plus 1, hence,
+ * subtracted 1 from the length field.
+ * As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f`
+ * represents 64-bytes to be transferred.
+ */
hsfc |= HSFC_FDBC_VAL(len - 1);
hsfc |= HSFC_FGO; /* start */
prettyprint_ich9_reg_hsfc(hsfc, ich_generation);
@@ -1403,7 +1409,7 @@
}
msg_pdbg("Reading Status register\n");
- if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 0, len, ich_generation,
+ if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 1, len, ich_generation,
hwseq_data->addr_mask)) {
msg_perr("Reading Status register failed\n!!");
return -1;
@@ -1426,7 +1432,7 @@
ich_fill_data(&value, len, ICH9_REG_FDATA0);
- if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 0, len, ich_generation,
+ if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 1, len, ich_generation,
hwseq_data->addr_mask)) {
msg_perr("Writing Status register failed\n!!");
return -1;
@@ -1522,7 +1528,7 @@
msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
- if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 0, ich_generation,
+ if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 1, ich_generation,
hwseq_data->addr_mask))
return -1;
return 0;
--
To view, visit https://review.coreboot.org/c/flashrom/+/69789
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I5b911655649c693e576497520687d7810bbd3c54
Gerrit-Change-Number: 69789
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-MessageType: newchange
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69788 )
Change subject: ichspi: Clear Fast SPI HSFC register before HW seq operation
......................................................................
ichspi: Clear Fast SPI HSFC register before HW seq operation
This patch fixes a regression introduced with
commit 7ed1337309d3fe74f5af09520970f0f1d417399a (ichspi: Factor out
common hwseq_xfer logic into helpers).
The reason for the regression is ignoring the fact that the Fast SPI
controller MMIO register HSFC (0x06) might not hold the default zero
value before initiating the HW sequencing operation.
Having a `1b` value in the HSFC.FDBC (bits 24-29) field would represent
a byte that needs to be transfered.
While debugging the regression, we have observed that the default value
in the FDBC (prior to initiate any operation) is 0x3f (instead of
zero) which represents 64-byte transfer.
localhost ~ # iotools mmio_read32 0x92d16006
0x3f00
<Fast SPI MMIO BAR: 0x92d16000 and HSFC offset: 0x06>
FDBC offset during `--wp-disable` operation represents higher numbers of
bytes than the actual and eventually results in the error.
BUG=b:258280679
TEST=Able to build flashrom and perform below operations on Google, Rex
and Google, Kano/Taeko.
Without this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x3f00
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (Read Status): 0x3f11
With this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x0
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (Read Status): 0x11
Additionally, verified other HW sequencing operations (like read, write,
erase, read status, write status, read ID) working fine without any
error.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98
---
M ichspi.c
1 file changed, 57 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/69788/1
diff --git a/ichspi.c b/ichspi.c
index 4e982f0..a3552d3 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1357,6 +1357,8 @@
/* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
+ /* make sure HSFC register is cleared before initiate any operation */
+ REGWRITE16(ICH9_REG_HSFC, 0);
/* Set up transaction parameters. */
hsfc = REGREAD16(ICH9_REG_HSFC);
--
To view, visit https://review.coreboot.org/c/flashrom/+/69788
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98
Gerrit-Change-Number: 69788
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-MessageType: newchange
Attention is currently required from: Alexander Goncharov.
Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68755 )
Change subject: tests: add probe lifecycle test for ch341a_spi
......................................................................
Patch Set 3: Code-Review+1
(2 comments)
File tests/ch341a_spi.c:
https://review.coreboot.org/c/flashrom/+/68755/comment/20f6cc04_a16e4b06
PS2, Line 26: struct libusb_transfer *transfer_in;
> OK, I've done it. […]
Yes, resolving
File tests/ch341a_spi.c:
https://review.coreboot.org/c/flashrom/+/68755/comment/e8d7d6cc_b94742a6
PS3, Line 26: /* Since the test transfers a data that fits in one CH341 packet, we
: don't need an array of these transfers (as is done in the driver code). */
Please align with code style: https://www.flashrom.org/Development_Guidelines#Coding_style
For the multi-line comment that is
/*
* comment
*/
--
To view, visit https://review.coreboot.org/c/flashrom/+/68755
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I0a2d5591d097435fc69719e1d9bd153433425821
Gerrit-Change-Number: 68755
Gerrit-PatchSet: 3
Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net>
Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net>
Gerrit-Comment-Date: Fri, 18 Nov 2022 09:15:12 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>
Comment-In-Reply-To: Alexander Goncharov <chat(a)joursoir.net>
Gerrit-MessageType: comment
Attention is currently required from: Felix Singer, Thomas Heijligen, Alexander Goncharov.
Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67664 )
Change subject: tests: add basic lifecycle test for ch341a_spi
......................................................................
Patch Set 9:
(4 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/67664/comment/995b9f45_5dd71834
PS9, Line 8:
If you could add test scenarios in commit message, that would be great. I know you run a few:
1) running test normally -> test pass
2) disabling the programmer ch341_spi -> test skipped, the rest of tests run normally
3) running with no libusb installed -> 3 tests skipped (dediprog, raiden_debug, ch341a), the rest of tests run normally
File tests/ch341a_spi.c:
https://review.coreboot.org/c/flashrom/+/67664/comment/c1ede016_424cdfb4
PS5, Line 22: transfer->status = LIBUSB_TRANSFER_COMPLETED;
: transfer->actual_length = transfer->length;
: transfer->callback(transfer);
> Finally, I've wrote :D
Marking as resolved!
File tests/libusb_wraps.c:
PS5:
> Okay I agree on that. Let's say we are introducing this as a default approach from now on. […]
Looks like you are ready to split the patch?
https://review.coreboot.org/c/flashrom/+/67664/comment/5c146483_33c0e555
PS5, Line 39: /* https://libusb.sourceforge.io/api-1.0/group__libusb__lib.html#ga5f8376b7a86… */
> Alright, thank you! I will just mark this unresolved so that you won't forget to remove links at the […]
I think the time has come, you can remove those
--
To view, visit https://review.coreboot.org/c/flashrom/+/67664
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: If28fbe09ad685082152aa3a7e8d5a150169aee9e
Gerrit-Change-Number: 67664
Gerrit-PatchSet: 9
Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net>
Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Attention: Thomas Heijligen <src(a)posteo.de>
Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net>
Gerrit-Comment-Date: Fri, 18 Nov 2022 09:05:50 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net>
Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>
Comment-In-Reply-To: Alexander Goncharov <chat(a)joursoir.net>
Gerrit-MessageType: comment
Attention is currently required from: Nikolai Artemiev, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk.
Hello build bot (Jenkins), Nikolai Artemiev, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69750
to look at the new patch set (#2).
Change subject: ichspi: Fix number of bytes for read, write, flash id, erase operation
......................................................................
ichspi: Fix number of bytes for read, write, flash id, erase operation
This patch fixes a potential issue where the SPI controller register
HSFC.FDBC (bits 24-29) value gets incorrectly calculated while passing
the `len` as `0` instead of `1`.
As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f`
represents 64-bytes to be transferred. The number of bytes
transferred is the value of this field plus 1.
If we would like to transfer 1 byte then we need to set `0b` in
FDBC for operations like read, write, flash id as to account for
`set byte count` hence, the `len` argument should be `1`.
Additionally, as per EDS, the FDBC field is ignored for any block
erase command.
Note: `FDBC` field still holds the non-zero default value before
any HW seq operation (which might impact the HW seq operations unless
cleared explicitly). An incremental patch on this train will fix
that observation too.
BUG=b:258280679
TEST=Able to build flashrom and perform below operations on Google,
Rex and Google, Kano/Taeko.
Without this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x3f00
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (--wp-disable): 0x3f11
With this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x300
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (--wp-disable): 0x311
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ie5de7c5bd9809d146a317df56996f7f8a85ca9a5
---
M ichspi.c
1 file changed, 51 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/50/69750/2
--
To view, visit https://review.coreboot.org/c/flashrom/+/69750
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Ie5de7c5bd9809d146a317df56996f7f8a85ca9a5
Gerrit-Change-Number: 69750
Gerrit-PatchSet: 2
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Nikolai Artemiev <nartemiev(a)chromium.org>
Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-MessageType: newpatchset
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69781
to look at the new patch set (#5).
Change subject: util/pkgbuilds: Add musl PKGBUILDs
......................................................................
util/pkgbuilds: Add musl PKGBUILDs
WIP
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Change-Id: I28f524a53897685ab763c48f8be5370b8f6488b6
---
A util/pkgbuilds/aarch64-linux-musl/PKGBUILD
A util/pkgbuilds/libusb/PKGBUILD
A util/pkgbuilds/riscv64-linux-musl/PKGBUILD
3 files changed, 142 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/69781/5
--
To view, visit https://review.coreboot.org/c/flashrom/+/69781
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I28f524a53897685ab763c48f8be5370b8f6488b6
Gerrit-Change-Number: 69781
Gerrit-PatchSet: 5
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69781
to look at the new patch set (#4).
Change subject: util/pkgbuilds: Add musl PKGBUILDs
......................................................................
util/pkgbuilds: Add musl PKGBUILDs
WIP
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Change-Id: I28f524a53897685ab763c48f8be5370b8f6488b6
---
A util/pkgbuilds/aarch64-linux-musl/PKGBUILD
A util/pkgbuilds/libusb/PKGBUILD
A util/pkgbuilds/riscv64-linux-musl/PKGBUILD
3 files changed, 142 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/69781/4
--
To view, visit https://review.coreboot.org/c/flashrom/+/69781
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I28f524a53897685ab763c48f8be5370b8f6488b6
Gerrit-Change-Number: 69781
Gerrit-PatchSet: 4
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/67700 )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: stlinkv3_spi: work around false-positive compiler error
......................................................................
stlinkv3_spi: work around false-positive compiler error
`stlinkv3_handle` is declared without an initial value. The variable
is initialized in a branch which can only be accessed if
`devs_stlinkv3_spi[0].vendor_id != 0`. Otherwise, the variable contains
a garbage value. We can consider this case as a false positive because
`devs_stlinkv3_spi` holds as a minimum one device entry (otherwise we
wouldn't need a driver).
This issue was found by setting compiler flag `-Og`, which optimizes
debugging experience, and running scan-build. So, we have to work
around it to allow the compiler to use the flag and remove the warning
from the scan-build list.
Change-Id: Ibaf25f67186724d9045ade849026782c3eac4952
Signed-off-by: Alexander Goncharov <chat(a)joursoir.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67700
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Thomas Heijligen <src(a)posteo.de>
Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org>
Reviewed-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M stlinkv3_spi.c
1 file changed, 30 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Felix Singer: Looks good to me, but someone else must approve
Thomas Heijligen: Looks good to me, approved
Angel Pons: Looks good to me, approved
Anastasia Klimchuk: Looks good to me, approved
diff --git a/stlinkv3_spi.c b/stlinkv3_spi.c
index 9ae3df5..1d5763b 100644
--- a/stlinkv3_spi.c
+++ b/stlinkv3_spi.c
@@ -482,7 +482,8 @@
int ret = 1;
int devIndex = 0;
struct libusb_context *usb_ctx;
- libusb_device_handle *stlinkv3_handle;
+ /* Initialize stlinkv3_handle to NULL for suppressing scan-build false positive core.uninitialized.Branch */
+ libusb_device_handle *stlinkv3_handle = NULL;
struct stlinkv3_spi_data *stlinkv3_data;
if (libusb_init(&usb_ctx)) {
--
To view, visit https://review.coreboot.org/c/flashrom/+/67700
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Ibaf25f67186724d9045ade849026782c3eac4952
Gerrit-Change-Number: 67700
Gerrit-PatchSet: 6
Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net>
Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Miklós Márton <martonmiklosqdev(a)gmail.com>
Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Nico Huber <nico.h(a)gmx.de>
Gerrit-MessageType: merged