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[M] Change in flashrom[master]: linux_mtd.c: Factor out detection phases from setup func
by Edward O'Callaghan (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Nikolai Artemiev. Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/73495 ) Change subject: linux_mtd.c: Factor out detection phases from setup func ...................................................................... linux_mtd.c: Factor out detection phases from setup func The setup phase function is performing detection logic, move this to a earlier phase in the init sequence such that it can be used seperately. Change-Id: I15915b71e1a030548c5f082cde78c42ece28bb37 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M linux_mtd.c 1 file changed, 70 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/73495/1 diff --git a/linux_mtd.c b/linux_mtd.c index b3be72a..708e340 100644 --- a/linux_mtd.c +++ b/linux_mtd.c @@ -443,57 +443,6 @@ .wp_get_ranges = linux_mtd_wp_get_available_ranges, }; -/* Returns 0 if setup is successful, non-zero to indicate error */ -static int linux_mtd_setup(int dev_num, struct linux_mtd_data *data) -{ - char sysfs_path[32]; - int ret = 1; - - /* Start by checking /sys/class/mtd/mtdN/type which should be "nor" for NOR flash */ - if (snprintf(sysfs_path, sizeof(sysfs_path), "%s/mtd%d/", LINUX_MTD_SYSFS_ROOT, dev_num) < 0) - goto linux_mtd_setup_exit; - - char buf[4] = { 0 }; - if (read_sysfs_string(sysfs_path, "type", buf, sizeof(buf))) - return 1; - - if (strcmp(buf, "nor")) { - msg_perr("MTD device %d type is not \"nor\"\n", dev_num); - goto linux_mtd_setup_exit; - } - - /* sysfs shows the correct device type, see if corresponding device node exists */ - char dev_path[32]; - struct stat s; - snprintf(dev_path, sizeof(dev_path), "%s/mtd%d", LINUX_DEV_ROOT, dev_num); - errno = 0; - if (stat(dev_path, &s) < 0) { - msg_pdbg("Cannot stat \"%s\": %s\n", dev_path, strerror(errno)); - goto linux_mtd_setup_exit; - } - - /* so far so good, get more info from other files in this dir */ - if (snprintf(sysfs_path, sizeof(sysfs_path), "%s/mtd%d/", LINUX_MTD_SYSFS_ROOT, dev_num) < 0) - goto linux_mtd_setup_exit; - if (get_mtd_info(sysfs_path, data)) - goto linux_mtd_setup_exit; - - /* open file stream and go! */ - if ((data->dev_fp = fopen(dev_path, "r+")) == NULL) { - msg_perr("Cannot open file stream for %s\n", dev_path); - goto linux_mtd_setup_exit; - } - ret = setvbuf(data->dev_fp, NULL, _IONBF, 0); - if (ret) - msg_pwarn("Failed to set MTD device to unbuffered: %d\n", ret); - - msg_pinfo("Opened %s successfully\n", dev_path); - - ret = 0; -linux_mtd_setup_exit: - return ret; -} - static int get_params(const struct programmer_cfg *cfg, int *dev_num) { char *param_str = extract_programmer_param_str(cfg, "dev"); @@ -516,17 +465,18 @@ return 0; } -static int check_sysfs_devnum_path(int dev_num) +static int detect_spinor_in_sysfs(int dev_num, char *dev_path, size_t dp_len) { + /* Start by checking /sys/class/mtd/mtdN/type which should be "nor" for NOR flash */ + char sysfs_path[32]; + if (snprintf(sysfs_path, sizeof(sysfs_path), "%s/mtd%d", LINUX_MTD_SYSFS_ROOT, dev_num) < 0) + return -1; + /* * If user specified the MTD device number then error out if it doesn't * appear to exist. Otherwise assume the error is benign and print a * debug message. Bail out in either case. */ - char sysfs_path[32]; - if (snprintf(sysfs_path, sizeof(sysfs_path), "%s/mtd%d", LINUX_MTD_SYSFS_ROOT, dev_num) < 0) - return -1; - struct stat s; if (stat(sysfs_path, &s) < 0) { if (dev_num) @@ -535,17 +485,64 @@ msg_pdbg("%s does not exist\n", sysfs_path); return -1; } + + /* Check sysfs shows the correct device type. */ + char buf[4] = { 0 }; + if (read_sysfs_string(sysfs_path, "type", buf, sizeof(buf))) + return -1; + + if (strcmp(buf, "nor")) { + msg_perr("MTD device %d type is not \"nor\"\n", dev_num); + return -1; + } + + /* Check if the corresponding device node exists. */ + snprintf(dev_path, dp_len, "%s/mtd%d", LINUX_DEV_ROOT, dev_num); + errno = 0; + if (stat(dev_path, &s) < 0) { + msg_pdbg("Cannot stat \"%s\": %s\n", dev_path, strerror(errno)); + return -1; + } + return 0; } +/* Returns 0 if setup is successful, non-zero to indicate error */ +static int linux_mtd_setup(int dev_num, const char *dev_path, struct linux_mtd_data *data) +{ + char sysfs_path[32]; + int ret = 1; + + /* Get more info from other files in the sysfs_path dir. */ + if (snprintf(sysfs_path, sizeof(sysfs_path), "%s/mtd%d/", LINUX_MTD_SYSFS_ROOT, dev_num) < 0) + goto linux_mtd_setup_exit; + if (get_mtd_info(sysfs_path, data)) + goto linux_mtd_setup_exit; + + /* open file stream and go! */ + if ((data->dev_fp = fopen(dev_path, "r+")) == NULL) { + msg_perr("Cannot open file stream for %s\n", dev_path); + goto linux_mtd_setup_exit; + } + ret = setvbuf(data->dev_fp, NULL, _IONBF, 0); + if (ret) + msg_pwarn("Failed to set MTD device to unbuffered: %d\n", ret); + + msg_pinfo("Opened %s successfully\n", dev_path); + + ret = 0; +linux_mtd_setup_exit: + return ret; +} + static int linux_mtd_init(const struct programmer_cfg *cfg) { int dev_num; - if (get_params(cfg, &dev_num) < 0) return 1; - if (check_sysfs_devnum_path(dev_num) < 0) + char dev_path[32]; + if (detect_spinor_in_sysfs(dev_num, dev_path, sizeof(dev_path)) < 0) return 1; struct linux_mtd_data *data = calloc(1, sizeof(*data)); @@ -555,7 +552,7 @@ } /* Get MTD info and store it in `data` */ - if (linux_mtd_setup(dev_num, data)) { + if (linux_mtd_setup(dev_num, dev_path, data)) { free(data); return 1; } -- To view, visit https://review.coreboot.org/c/flashrom/+/73495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I15915b71e1a030548c5f082cde78c42ece28bb37 Gerrit-Change-Number: 73495 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: linux_mtd.c: Split linux_mtd_init() into sub-functions
by Edward O'Callaghan (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Nikolai Artemiev. Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/73494 ) Change subject: linux_mtd.c: Split linux_mtd_init() into sub-functions ...................................................................... linux_mtd.c: Split linux_mtd_init() into sub-functions Here we split up the linux_mtd_init() entry-point into its constituent phases; get_params -> check_sysfs_path -> alloc resources -> setup drv -> register. The motivation is that we wish for linux_mtd to have a pre_init hook for the purposes of detection only. This is a requirement for the internal programmer via the current try_mtd() hack. Change-Id: Ic81068adbc7da8b28de07a161b5cec2fff0fce49 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M linux_mtd.c 1 file changed, 56 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/73494/1 diff --git a/linux_mtd.c b/linux_mtd.c index 495db9a..b3be72a 100644 --- a/linux_mtd.c +++ b/linux_mtd.c @@ -494,26 +494,30 @@ return ret; } -static int linux_mtd_init(const struct programmer_cfg *cfg) +static int get_params(const struct programmer_cfg *cfg, int *dev_num) { - char *param_str; - int dev_num = 0; - int ret = 1; - struct linux_mtd_data *data = NULL; - - param_str = extract_programmer_param_str(cfg, "dev"); - if (param_str) { - char *endptr; - - dev_num = strtol(param_str, &endptr, 0); - if ((*endptr != '\0') || (dev_num < 0)) { - msg_perr("Invalid device number %s. Use flashrom -p " - "linux_mtd:dev=N where N is a valid MTD\n" - "device number.\n", param_str); - goto linux_mtd_init_exit; - } + char *param_str = extract_programmer_param_str(cfg, "dev"); + if (!param_str) { + *dev_num = 0; + return 0; } + char *endptr; + *dev_num = strtol(param_str, &endptr, 0); + if ((*endptr != '\0') || (*dev_num < 0)) { + msg_perr("Invalid device number %s. Use flashrom -p " + "linux_mtd:dev=N where N is a valid MTD\n" + "device number.\n", param_str); + free(param_str); + return -1; + } + + free(param_str); + return 0; +} + +static int check_sysfs_devnum_path(int dev_num) +{ /* * If user specified the MTD device number then error out if it doesn't * appear to exist. Otherwise assume the error is benign and print a @@ -521,19 +525,30 @@ */ char sysfs_path[32]; if (snprintf(sysfs_path, sizeof(sysfs_path), "%s/mtd%d", LINUX_MTD_SYSFS_ROOT, dev_num) < 0) - goto linux_mtd_init_exit; + return -1; struct stat s; if (stat(sysfs_path, &s) < 0) { - if (param_str) + if (dev_num) msg_perr("%s does not exist\n", sysfs_path); else msg_pdbg("%s does not exist\n", sysfs_path); - goto linux_mtd_init_exit; + return -1; } - free(param_str); + return 0; +} - data = calloc(1, sizeof(*data)); +static int linux_mtd_init(const struct programmer_cfg *cfg) +{ + int dev_num; + + if (get_params(cfg, &dev_num) < 0) + return 1; + + if (check_sysfs_devnum_path(dev_num) < 0) + return 1; + + struct linux_mtd_data *data = calloc(1, sizeof(*data)); if (!data) { msg_perr("Unable to allocate memory for linux_mtd_data\n"); return 1; @@ -546,10 +561,6 @@ } return register_opaque_master(&linux_mtd_opaque_master, data); - -linux_mtd_init_exit: - free(param_str); - return ret; } const struct programmer_entry programmer_linux_mtd = { -- To view, visit https://review.coreboot.org/c/flashrom/+/73494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic81068adbc7da8b28de07a161b5cec2fff0fce49 Gerrit-Change-Number: 73494 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: tree/: Move max_rom_decode into board_cfg
by Edward O'Callaghan (Code Review) 06 Mar '23

06 Mar '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/73493 ) Change subject: tree/: Move max_rom_decode into board_cfg ...................................................................... tree/: Move max_rom_decode into board_cfg TEST=`./flashrom -p internal --flash-name`. Change-Id: Ifa077d867f29ca7bf9c47529a9cd23273badec94 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M atapromise.c M board_enable.c M chipset_enable.c M cli_classic.c M drkaiser.c M flashrom.c M include/programmer.h M it8212.c M nic3com.c M nicintel.c M nicnatsemi.c M satamv.c M wbsio_spi.c 13 files changed, 57 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/73493/1 diff --git a/atapromise.c b/atapromise.c index 9beebf1..3cd24bb 100644 --- a/atapromise.c +++ b/atapromise.c @@ -169,7 +169,7 @@ data->bar = bar; data->rom_size = rom_size; - max_rom_decode.parallel = rom_size; + cfg->bcfg->max_rom_decode.parallel = rom_size; return register_par_master(&par_master_atapromise, BUS_PARALLEL, data); } diff --git a/board_enable.c b/board_enable.c index efb4131..e45ab48 100644 --- a/board_enable.c +++ b/board_enable.c @@ -620,16 +620,16 @@ msg_pdbg("Enabling IT8705F flash ROM interface write.\n"); if (tmp & 0x02) { /* The data sheet contradicts itself about max size. */ - max_rom_decode.parallel = 1024 * 1024; + bcfg->max_rom_decode.parallel = 1024 * 1024; msg_pinfo("IT8705F with very unusual settings.\n" "Please send the output of \"flashrom -V -p internal\" to flashrom(a)flashrom.org\n" "with \"IT8705: your board name: flashrom -V\" as the subject to help us finish\n" "support for your Super I/O. Thanks.\n"); ret = 1; } else if (tmp & 0x08) { - max_rom_decode.parallel = 512 * 1024; + bcfg->max_rom_decode.parallel = 512 * 1024; } else { - max_rom_decode.parallel = 256 * 1024; + bcfg->max_rom_decode.parallel = 256 * 1024; } /* Safety checks. The data sheet is unclear here: Segments 1+3 * overlap, no segment seems to cover top - 1MB to top - 512kB. @@ -673,7 +673,7 @@ ret = 1; } msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n", - max_rom_decode.parallel); + bcfg->max_rom_decode.parallel); if (ret) { msg_pinfo("Not enabling IT8705F flash write.\n"); } else { @@ -2765,7 +2765,7 @@ /* limit the maximum size of the parallel bus */ if (board->max_rom_decode_parallel) - max_rom_decode.parallel = board->max_rom_decode_parallel * 1024; + cfg->max_rom_decode.parallel = board->max_rom_decode_parallel * 1024; if (board->enable) { msg_pinfo("Enabling full flash access for board \"%s %s\"... ", diff --git a/chipset_enable.c b/chipset_enable.c index 84206b2..c93480e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -549,8 +549,8 @@ contiguous = 0; } } - max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); - msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh); + cfg->bcfg->max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); + msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", cfg->bcfg->max_rom_decode.fwh); return 0; } @@ -1239,18 +1239,18 @@ reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG); if (reg8 & CS5530_ISA_MASTER) { /* We have A0-A23 available. */ - max_rom_decode.parallel = 16 * 1024 * 1024; + cfg->bcfg->max_rom_decode.parallel = 16 * 1024 * 1024; } else { reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG); if (reg8 & CS5530_ENABLE_SA2320) { /* We have A0-19, A20-A23 available. */ - max_rom_decode.parallel = 16 * 1024 * 1024; + cfg->bcfg->max_rom_decode.parallel = 16 * 1024 * 1024; } else if (reg8 & CS5530_ENABLE_SA20) { /* We have A0-19, A20 available. */ - max_rom_decode.parallel = 2 * 1024 * 1024; + cfg->bcfg->max_rom_decode.parallel = 2 * 1024 * 1024; } else { /* A20 and above are not active. */ - max_rom_decode.parallel = 1024 * 1024; + cfg->bcfg->max_rom_decode.parallel = 1024 * 1024; } } @@ -1356,14 +1356,14 @@ static int enable_flash_amd_768_8111(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { /* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */ - max_rom_decode.lpc = 5 * 1024 * 1024; + cfg->bcfg->max_rom_decode.lpc = 5 * 1024 * 1024; return enable_flash_amd_via(cfg, dev, name, 0xC0); } static int enable_flash_vt82c586(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */ - max_rom_decode.parallel = 512 * 1024; + cfg->bcfg->max_rom_decode.parallel = 512 * 1024; return enable_flash_amd_via(cfg, dev, name, 0xC0); } @@ -1371,7 +1371,7 @@ static int enable_flash_vt82c596(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { /* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */ - max_rom_decode.parallel = 1024 * 1024; + cfg->bcfg->max_rom_decode.parallel = 1024 * 1024; return enable_flash_amd_via(cfg, dev, name, 0xE0); } diff --git a/cli_classic.c b/cli_classic.c index da68919..96e0b81 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -524,43 +524,43 @@ /* Returns the number of buses commonly supported by the current programmer and flash chip where the latter * can not be completely accessed due to size/address limits of the programmer. */ static unsigned int count_max_decode_exceedings(const struct flashctx *flash, - const struct decode_sizes *max_rom_decode_) + const struct decode_sizes *max_rom_decode) { unsigned int limitexceeded = 0; uint32_t size = flash->chip->total_size * 1024; enum chipbustype buses = flash->mst->buses_supported & flash->chip->bustype; - if ((buses & BUS_PARALLEL) && (max_rom_decode_->parallel < size)) { + if ((buses & BUS_PARALLEL) && (max_rom_decode->parallel < size)) { limitexceeded++; msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, - max_rom_decode_->parallel / 1024, "Parallel"); + max_rom_decode->parallel / 1024, "Parallel"); } - if ((buses & BUS_LPC) && (max_rom_decode_->lpc < size)) { + if ((buses & BUS_LPC) && (max_rom_decode->lpc < size)) { limitexceeded++; msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, - max_rom_decode_->lpc / 1024, "LPC"); + max_rom_decode->lpc / 1024, "LPC"); } - if ((buses & BUS_FWH) && (max_rom_decode_->fwh < size)) { + if ((buses & BUS_FWH) && (max_rom_decode->fwh < size)) { limitexceeded++; msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, - max_rom_decode_->fwh / 1024, "FWH"); + max_rom_decode->fwh / 1024, "FWH"); } - if ((buses & BUS_SPI) && (max_rom_decode_->spi < size)) { + if ((buses & BUS_SPI) && (max_rom_decode->spi < size)) { limitexceeded++; msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, - max_rom_decode_->spi / 1024, "SPI"); + max_rom_decode->spi / 1024, "SPI"); } return limitexceeded; } @@ -1064,7 +1064,7 @@ print_chip_support_status(fill_flash->chip); - unsigned int limitexceeded = count_max_decode_exceedings(fill_flash, &max_rom_decode); + unsigned int limitexceeded = count_max_decode_exceedings(fill_flash, &g_max_rom_decode); if (limitexceeded > 0 && !force) { enum chipbustype commonbuses = fill_flash->mst->buses_supported & fill_flash->chip->bustype; diff --git a/drkaiser.c b/drkaiser.c index ebf5119..36c9a01 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -106,7 +106,7 @@ data->flash_access = pci_read_word(dev, PCI_MAGIC_DRKAISER_ADDR); pci_write_word(dev, PCI_MAGIC_DRKAISER_ADDR, PCI_MAGIC_DRKAISER_VALUE); - max_rom_decode.parallel = 128 * 1024; + cfg->bcfg->max_rom_decode.parallel = 128 * 1024; return register_par_master(&par_master_drkaiser, BUS_PARALLEL, data); } diff --git a/flashrom.c b/flashrom.c index f2ee3a9..a9d34f1 100644 --- a/flashrom.c +++ b/flashrom.c @@ -45,7 +45,7 @@ * Programmers supporting multiple buses can have differing size limits on * each bus. Store the limits for each bus in a common struct. */ -struct decode_sizes max_rom_decode; +struct decode_sizes g_max_rom_decode; /* If nonzero, used as the start address of bottom-aligned flash. */ unsigned long flashbase; @@ -131,7 +131,7 @@ programmer = prog; /* Initialize all programmer specific data. */ /* Default to unlimited decode sizes. */ - max_rom_decode = (const struct decode_sizes) { + g_max_rom_decode = (const struct decode_sizes) { .parallel = 0xffffffff, .lpc = 0xffffffff, .fwh = 0xffffffff, @@ -144,8 +144,8 @@ /* Default to allowing writes. Broken programmers set this to 0. */ programmer_may_write = true; - struct board_cfg bcfg = {0}; - struct programmer_cfg cfg = { .bcfg = &bcfg }; + struct board_cfg bcfg = { .max_rom_decode = g_max_rom_decode }; + struct programmer_cfg cfg = { .bcfg = &bcfg, }; if (param) { cfg.params = strdup(param); diff --git a/include/programmer.h b/include/programmer.h index 2477c80..0f60767 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -158,6 +158,13 @@ extern const struct penable chipset_enables[]; +struct decode_sizes { + uint32_t parallel; + uint32_t lpc; + uint32_t fwh; + uint32_t spi; +}; + enum board_match_phase { P1, P2, @@ -168,6 +175,7 @@ int is_laptop; bool laptop_ok; enum chipbustype internal_buses_supported; + struct decode_sizes max_rom_decode; }; struct board_match { @@ -283,14 +291,8 @@ /* flashrom.c */ -struct decode_sizes { - uint32_t parallel; - uint32_t lpc; - uint32_t fwh; - uint32_t spi; -}; // FIXME: These need to be local, not global -extern struct decode_sizes max_rom_decode; +extern struct decode_sizes g_max_rom_decode; extern bool programmer_may_write; extern unsigned long flashbase; char *extract_programmer_param_str(const struct programmer_cfg *cfg, const char *param_name); diff --git a/it8212.c b/it8212.c index 3c1161d..6cee140 100644 --- a/it8212.c +++ b/it8212.c @@ -97,7 +97,7 @@ data->decode_access = pci_read_long(dev, PCI_ROM_ADDRESS); pci_write_long(dev, PCI_ROM_ADDRESS, io_base_addr | 0x01); - max_rom_decode.parallel = IT8212_MEMMAP_SIZE; + cfg->bcfg->max_rom_decode.parallel = IT8212_MEMMAP_SIZE; return register_par_master(&par_master_it8212, BUS_PARALLEL, data); } const struct programmer_entry programmer_it8212 = { diff --git a/nic3com.c b/nic3com.c index a578d48..25ec05c 100644 --- a/nic3com.c +++ b/nic3com.c @@ -142,7 +142,7 @@ data->internal_conf = internal_conf; data->id = id; - max_rom_decode.parallel = 128 * 1024; + cfg->bcfg->max_rom_decode.parallel = 128 * 1024; return register_par_master(&par_master_nic3com, BUS_PARALLEL, data); diff --git a/nicintel.c b/nicintel.c index feb07b6..0e700b6 100644 --- a/nicintel.c +++ b/nicintel.c @@ -118,7 +118,7 @@ data->nicintel_bar = bar; data->nicintel_control_bar = control_bar; - max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; + cfg->bcfg->max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; return register_par_master(&par_master_nicintel, BUS_PARALLEL, data); } diff --git a/nicnatsemi.c b/nicnatsemi.c index 65377dc..f0bfd0b 100644 --- a/nicnatsemi.c +++ b/nicnatsemi.c @@ -111,7 +111,7 @@ * max_rom_decode.parallel = 65536; and the mask in the read/write * functions below wants to be 0x0000FFFF. */ - max_rom_decode.parallel = 131072; + cfg->bcfg->max_rom_decode.parallel = 131072; return register_par_master(&par_master_nicnatsemi, BUS_PARALLEL, data); } diff --git a/satamv.c b/satamv.c index fea4c2b..8a0cebf 100644 --- a/satamv.c +++ b/satamv.c @@ -196,7 +196,7 @@ /* 512 kByte with two 8-bit latches, and * 4 MByte with additional 3-bit latch. */ - max_rom_decode.parallel = 4 * 1024 * 1024; + cfg->bcfg->max_rom_decode.parallel = 4 * 1024 * 1024; return register_par_master(&par_master_satamv, BUS_PARALLEL, data); } diff --git a/wbsio_spi.c b/wbsio_spi.c index 9f33b18..d779012 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -206,7 +206,7 @@ msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 kB!\n", __func__); - max_rom_decode.spi = 1024 * 1024; + cfg->max_rom_decode.spi = 1024 * 1024; struct wbsio_spi_data *data = calloc(1, sizeof(*data)); if (!data) { -- To view, visit https://review.coreboot.org/c/flashrom/+/73493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ifa077d867f29ca7bf9c47529a9cd23273badec94 Gerrit-Change-Number: 73493 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: flashrom,internal: Move board_cfg up in the CFG to prog_init
by Edward O'Callaghan (Code Review) 06 Mar '23

06 Mar '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/73492 ) Change subject: flashrom,internal: Move board_cfg up in the CFG to prog_init ...................................................................... flashrom,internal: Move board_cfg up in the CFG to prog_init Avoid the need for a copy of the programmer_cfg within the internal programmer. Move the board_cfg up into programmer_init(). TEST=`$ ./flashrom -p internal --flash-name`. Change-Id: I30bc4eefeb589d3ee7827fcfea81985292c88a10 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M flashrom.c M internal.c 2 files changed, 29 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/73492/1 diff --git a/flashrom.c b/flashrom.c index da46354..f2ee3a9 100644 --- a/flashrom.c +++ b/flashrom.c @@ -144,7 +144,8 @@ /* Default to allowing writes. Broken programmers set this to 0. */ programmer_may_write = true; - struct programmer_cfg cfg; + struct board_cfg bcfg = {0}; + struct programmer_cfg cfg = { .bcfg = &bcfg }; if (param) { cfg.params = strdup(param); diff --git a/internal.c b/internal.c index bba7043..f2fff0d 100644 --- a/internal.c +++ b/internal.c @@ -149,7 +149,6 @@ const char *cb_model = NULL; #endif bool force_boardenable = false; - struct board_cfg bcfg = {0}; ret = get_params(cfg, &force_boardenable, &force_boardmismatch, @@ -162,7 +161,7 @@ * is found, the host controller init routine sets the * internal_buses_supported bitfield. */ - bcfg.internal_buses_supported = BUS_NONSPI; + cfg->bcfg->internal_buses_supported = BUS_NONSPI; if (try_mtd(cfg) == 0) { ret = 0; @@ -201,12 +200,12 @@ } } - bcfg.is_laptop = 2; /* Assume that we don't know by default. */ + cfg->bcfg->is_laptop = 2; /* Assume that we don't know by default. */ - dmi_init(&bcfg.is_laptop); + dmi_init(&(cfg->bcfg->is_laptop)); /* In case Super I/O probing would cause pretty explosions. */ - board_handle_before_superio(&bcfg, force_boardenable); + board_handle_before_superio(cfg->bcfg, force_boardenable); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); @@ -219,22 +218,21 @@ #endif /* Check laptop whitelist. */ - board_handle_before_laptop(&bcfg, force_boardenable); + board_handle_before_laptop(cfg->bcfg, force_boardenable); /* * Disable all internal buses by default if we are not sure * this isn't a laptop. Board-enables may override this, * non-legacy buses (SPI and opaque atm) are probed anyway. */ - if (bcfg.is_laptop && !(bcfg.laptop_ok || force_laptop || (not_a_laptop && bcfg.is_laptop == 2))) - bcfg.internal_buses_supported = BUS_NONE; + if (cfg->bcfg->is_laptop && !(cfg->bcfg->laptop_ok || + force_laptop || (not_a_laptop && cfg->bcfg->is_laptop == 2))) + cfg->bcfg->internal_buses_supported = BUS_NONE; /* try to enable it. Failure IS an option, since not all motherboards * really need this to be done, etc., etc. */ - struct programmer_cfg icfg = *cfg; - icfg.bcfg = &bcfg; - ret = chipset_flash_enable(&icfg); + ret = chipset_flash_enable(cfg); if (ret == -2) { msg_perr("WARNING: No chipset found. Flash detection " "will most likely fail.\n"); @@ -247,7 +245,7 @@ * parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */ init_superio_ite(cfg); - if (board_flash_enable(&bcfg, + if (board_flash_enable(cfg->bcfg, board_vendor, board_model, cb_vendor, cb_model, force_boardenable)) { msg_perr("Aborting to be safe.\n"); ret = 1; @@ -255,10 +253,10 @@ } #endif - internal_par_init(bcfg.internal_buses_supported); + internal_par_init(cfg->bcfg->internal_buses_supported); /* Report if a non-whitelisted laptop is detected that likely uses a legacy bus. */ - report_nonwl_laptop_detected(&bcfg); + report_nonwl_laptop_detected(cfg->bcfg); ret = 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/73492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I30bc4eefeb589d3ee7827fcfea81985292c88a10 Gerrit-Change-Number: 73492 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

1 0

[M] Change in flashrom[master]: internal: Move laptop_ok into board_cfg
by Edward O'Callaghan (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Thomas Heijligen, Angel Pons. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/73456 ) Change subject: internal: Move laptop_ok into board_cfg ...................................................................... Patch Set 2: (1 comment) File internal.c: https://review.coreboot.org/c/flashrom/+/73456/comment/082790bb_9b72befa PS1, Line 158: : /* Unconditionally reset global state from previous operation. */ : bcfg.laptop_ok = false; > actually can delete this now. Ack -- To view, visit https://review.coreboot.org/c/flashrom/+/73456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I459215253845c2af73262943ce91a36464e9eb06 Gerrit-Change-Number: 73456 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 06:20:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

1 0

[M] Change in flashrom[master]: tree/: Remove internal_buses_support from global scope
by Edward O'Callaghan (Code Review) 06 Mar '23

06 Mar '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/73464 ) Change subject: tree/: Remove internal_buses_support from global scope ...................................................................... tree/: Remove internal_buses_support from global scope Finally the buses_supported by the internal programmer can be packed up into the board_cfg substructure and out of the global symbol scope. TEST=`$ sudo ./flashrom -p internal --flash-name`. Change-Id: I987f2726acbf78e0294f8977f5a1734d2350405e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M board_enable.c M chipset_enable.c M ichspi.c M include/programmer.h M internal.c M internal_par.c M it87spi.c 7 files changed, 38 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/73464/1 diff --git a/board_enable.c b/board_enable.c index 1ed1c5d..efb4131 100644 --- a/board_enable.c +++ b/board_enable.c @@ -606,7 +606,7 @@ uint8_t tmp; int ret = 0; - if (!(internal_buses_supported & BUS_PARALLEL)) + if (!(bcfg->internal_buses_supported & BUS_PARALLEL)) return 1; enter_conf_mode_ite(port); @@ -614,7 +614,7 @@ /* Check if at least one flash segment is enabled. */ if (tmp & 0xf0) { /* The IT8705F will respond to LPC cycles and translate them. */ - internal_buses_supported &= BUS_PARALLEL; + bcfg->internal_buses_supported &= BUS_PARALLEL; /* Flash ROM I/F Writes Enable */ tmp |= 0x04; msg_pdbg("Enabling IT8705F flash ROM interface write.\n"); diff --git a/chipset_enable.c b/chipset_enable.c index 0747d57..84206b2 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -72,13 +72,13 @@ tmp = pci_read_byte(dev, 0x40) & 0x3; switch (tmp) { case 3: - internal_buses_supported &= BUS_FWH; + cfg->bcfg->internal_buses_supported &= BUS_FWH; break; case 2: - internal_buses_supported &= BUS_LPC; + cfg->bcfg->internal_buses_supported &= BUS_LPC; break; default: - internal_buses_supported &= BUS_PARALLEL; + cfg->bcfg->internal_buses_supported &= BUS_PARALLEL; break; } @@ -228,7 +228,7 @@ uint16_t old, new; uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ - internal_buses_supported &= BUS_PARALLEL; + cfg->bcfg->internal_buses_supported &= BUS_PARALLEL; old = pci_read_word(dev, xbcs); @@ -563,7 +563,7 @@ if ((err = enable_flash_ich_fwh_decode(cfg, dev, ich_generation)) != 0) return err; - internal_buses_supported &= BUS_FWH; + cfg->bcfg->internal_buses_supported &= BUS_FWH; return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl); } @@ -1064,7 +1064,7 @@ if (ret_fwh == ERROR_FLASHROM_FATAL) return ret_fwh; - internal_buses_supported &= BUS_FWH; + cfg->bcfg->internal_buses_supported &= BUS_FWH; /* Get physical address of SPI Base Address and map it */ uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00; @@ -1218,7 +1218,7 @@ #define CS5530_ENABLE_SA2320 (1 << 2) #define CS5530_ENABLE_SA20 (1 << 6) - internal_buses_supported &= BUS_PARALLEL; + cfg->bcfg->internal_buses_supported &= BUS_PARALLEL; /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB. * FIXME: Should we really touch the low mapping below 1 MB? Flashrom @@ -1406,7 +1406,7 @@ msg_pdbg("done.\n"); } - internal_buses_supported &= BUS_LPC | BUS_FWH; + cfg->bcfg->internal_buses_supported &= BUS_LPC | BUS_FWH; ret = sb600_probe_spi(cfg, dev); @@ -1554,7 +1554,7 @@ { uint8_t tmp; - internal_buses_supported &= BUS_PARALLEL; + cfg->bcfg->internal_buses_supported &= BUS_PARALLEL; tmp = INB(0xc06); tmp |= 0x1; @@ -1643,7 +1643,7 @@ switch ((val >> 5) & 0x3) { case 0x0: ret = enable_flash_mcp55(cfg, dev, name); - internal_buses_supported &= BUS_LPC; + cfg->bcfg->internal_buses_supported &= BUS_LPC; msg_pdbg("Flash bus type is LPC\n"); break; case 0x2: @@ -1651,12 +1651,12 @@ /* SPI is added in mcp6x_spi_init if it works. * Do we really want to disable LPC in this case? */ - internal_buses_supported = BUS_NONE; + cfg->bcfg->internal_buses_supported = BUS_NONE; msg_pdbg("Flash bus type is SPI\n"); break; default: /* Should not happen. */ - internal_buses_supported = BUS_NONE; + cfg->bcfg->internal_buses_supported = BUS_NONE; msg_pwarn("Flash bus type is unknown (none)\n"); msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to\n" "flashrom(a)flashrom.org with \"your board name: flashrom -V\" as the subject to\n" @@ -2229,7 +2229,7 @@ "flashrom(a)flashrom.org including a verbose " "(-V) log.\nThank you!\n"); } - if (!(chipset_enables[i].buses & (internal_buses_supported | BUS_SPI))) { + if (!(chipset_enables[i].buses & (cfg->bcfg->internal_buses_supported | BUS_SPI))) { msg_pdbg("Skipping chipset enable: No supported buses enabled.\n"); continue; } diff --git a/ichspi.c b/ichspi.c index 0d3dd0e..d8f0196 100644 --- a/ichspi.c +++ b/ichspi.c @@ -2394,7 +2394,7 @@ /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */ /* Not sure if it speaks all these bus protocols. */ - internal_buses_supported &= BUS_LPC | BUS_FWH; + cfg->bcfg->internal_buses_supported &= BUS_LPC | BUS_FWH; ich_generation = CHIPSET_ICH7; register_spi_master(&spi_master_via, NULL); diff --git a/include/programmer.h b/include/programmer.h index 97c5e81..2477c80 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -167,6 +167,7 @@ struct board_cfg { int is_laptop; bool laptop_ok; + enum chipbustype internal_buses_supported; }; struct board_match { @@ -275,7 +276,6 @@ extern bool force_boardmismatch; void probe_superio(void); int register_superio(struct superio s); -extern enum chipbustype internal_buses_supported; #endif /* bitbang_spi.c */ diff --git a/internal.c b/internal.c index 071ea51..bba7043 100644 --- a/internal.c +++ b/internal.c @@ -29,8 +29,6 @@ bool force_boardmismatch = false; -enum chipbustype internal_buses_supported = BUS_NONE; - static int get_params(const struct programmer_cfg *cfg, bool *boardenable, bool *boardmismatch, @@ -164,7 +162,7 @@ * is found, the host controller init routine sets the * internal_buses_supported bitfield. */ - internal_buses_supported = BUS_NONSPI; + bcfg.internal_buses_supported = BUS_NONSPI; if (try_mtd(cfg) == 0) { ret = 0; @@ -229,7 +227,7 @@ * non-legacy buses (SPI and opaque atm) are probed anyway. */ if (bcfg.is_laptop && !(bcfg.laptop_ok || force_laptop || (not_a_laptop && bcfg.is_laptop == 2))) - internal_buses_supported = BUS_NONE; + bcfg.internal_buses_supported = BUS_NONE; /* try to enable it. Failure IS an option, since not all motherboards * really need this to be done, etc., etc. @@ -257,7 +255,7 @@ } #endif - internal_par_init(internal_buses_supported); + internal_par_init(bcfg.internal_buses_supported); /* Report if a non-whitelisted laptop is detected that likely uses a legacy bus. */ report_nonwl_laptop_detected(&bcfg); diff --git a/internal_par.c b/internal_par.c index e8e387c..031123e 100644 --- a/internal_par.c +++ b/internal_par.c @@ -75,5 +75,5 @@ void internal_par_init(enum chipbustype buses) { if (buses & BUS_NONSPI) - register_par_master(&par_master_internal, internal_buses_supported, NULL); + register_par_master(&par_master_internal, buses, NULL); } diff --git a/it87spi.c b/it87spi.c index dd9ab71..9e231f5 100644 --- a/it87spi.c +++ b/it87spi.c @@ -435,7 +435,7 @@ data->flashport = flashport; data->fast_spi = true; - if (internal_buses_supported & BUS_SPI) + if (cfg->bcfg->internal_buses_supported & BUS_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); /* FIXME: Add the SPI bus or replace the other buses with it? */ return register_spi_master(&spi_master_it87xx, data); -- To view, visit https://review.coreboot.org/c/flashrom/+/73464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I987f2726acbf78e0294f8977f5a1734d2350405e Gerrit-Change-Number: 73464 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

1 0

[S] Change in flashrom[master]: it87spi.c: Plumb board_cfg to it8705f_write_enable() entry
by Edward O'Callaghan (Code Review) 06 Mar '23

06 Mar '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/73463 ) Change subject: it87spi.c: Plumb board_cfg to it8705f_write_enable() entry ...................................................................... it87spi.c: Plumb board_cfg to it8705f_write_enable() entry Change-Id: Ia48d4d4acd02550c72ee46bfe4042b3c75941da0 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M board_enable.c M include/programmer.h M it87spi.c 3 files changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/63/73463/1 diff --git a/board_enable.c b/board_enable.c index d9af44e..1ed1c5d 100644 --- a/board_enable.c +++ b/board_enable.c @@ -601,7 +601,7 @@ * Suited for all boards with ITE IT8705F. * The SIS950 Super I/O probably requires a similar flash write enable. */ -int it8705f_write_enable(uint8_t port) +int it8705f_write_enable(struct board_cfg *bcfg, uint8_t port) { uint8_t tmp; int ret = 0; diff --git a/include/programmer.h b/include/programmer.h index e81d3bd..97c5e81 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -231,7 +231,7 @@ void w836xx_ext_enter(uint16_t port); void w836xx_ext_leave(uint16_t port); void probe_superio_winbond(void); -int it8705f_write_enable(uint8_t port); +int it8705f_write_enable(struct board_cfg *bcfg, uint8_t port); uint8_t sio_read(uint16_t port, uint8_t reg); void sio_write(uint16_t port, uint8_t reg, uint8_t data); void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); diff --git a/it87spi.c b/it87spi.c index 9c64659..dd9ab71 100644 --- a/it87spi.c +++ b/it87spi.c @@ -452,7 +452,7 @@ switch (superios[i].model) { case 0x8705: - ret |= it8705f_write_enable(superios[i].port); + ret |= it8705f_write_enable(cfg->bcfg, superios[i].port); break; case 0x8686: case 0x8716: -- To view, visit https://review.coreboot.org/c/flashrom/+/73463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia48d4d4acd02550c72ee46bfe4042b3c75941da0 Gerrit-Change-Number: 73463 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

1 0

[S] Change in flashrom[master]: ichspi: Plumb programmer_cfg to via_init_spi() entry
by Edward O'Callaghan (Code Review) 06 Mar '23

06 Mar '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/73462 ) Change subject: ichspi: Plumb programmer_cfg to via_init_spi() entry ...................................................................... ichspi: Plumb programmer_cfg to via_init_spi() entry Change-Id: I965645432a2d077fbdb3c4cdc36d008a5846ff8d Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M chipset_enable.c M ichspi.c M include/programmer.h 3 files changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/73462/1 diff --git a/chipset_enable.c b/chipset_enable.c index 16ef0f4..0747d57 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1193,12 +1193,12 @@ return ERROR_FLASHROM_FATAL; } - return via_init_spi(spi0_mm_base); + return via_init_spi(cfg, spi0_mm_base); } static int enable_flash_vt8237s_spi(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return via_init_spi(pci_read_long(dev, 0xbc) << 8); + return via_init_spi(cfg, pci_read_long(dev, 0xbc) << 8); } static int enable_flash_cs5530(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) diff --git a/ichspi.c b/ichspi.c index 1522d2b..0d3dd0e 100644 --- a/ichspi.c +++ b/ichspi.c @@ -2384,7 +2384,7 @@ .probe_opcode = ich_spi_probe_opcode, }; -int via_init_spi(uint32_t mmio_base) +int via_init_spi(const struct programmer_cfg *cfg, uint32_t mmio_base) { int i; diff --git a/include/programmer.h b/include/programmer.h index 5b304f5..e81d3bd 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -368,7 +368,7 @@ /* ichspi.c */ #if CONFIG_INTERNAL == 1 int ich_init_spi(const struct programmer_cfg *cfg, void *spibar, enum ich_chipset ich_generation); -int via_init_spi(uint32_t mmio_base); +int via_init_spi(const struct programmer_cfg *cfg, uint32_t mmio_base); /* amd_imc.c */ int amd_imc_shutdown(struct pci_dev *dev); -- To view, visit https://review.coreboot.org/c/flashrom/+/73462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I965645432a2d077fbdb3c4cdc36d008a5846ff8d Gerrit-Change-Number: 73462 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

1 0

[M] Change in flashrom[master]: internal: Move laptop_ok into board_cfg
by Edward O'Callaghan (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Thomas Heijligen, Angel Pons. Hello build bot (Jenkins), Thomas Heijligen, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/73456 to look at the new patch set (#2). Change subject: internal: Move laptop_ok into board_cfg ...................................................................... internal: Move laptop_ok into board_cfg Due to how internal is structured around chipset_flash_enable() entry we need to prepare a crafted programmer_cfg that contains a board_enable substructure with data derived from the board_enable subsystem. While this is certainly not perfection, it does make clear the relationships between board_enable into chipset_flash_enable and subsequently the overall internal programmer initialisation in a RAII fashion at the type level over closure upon global state that is impossible to reason about. Also flip predicate in report_nonwl_laptop_detected() and return early with the trivial base-case. TEST=`$ sudo ./flashrom -p internal --flash-name`. Change-Id: I459215253845c2af73262943ce91a36464e9eb06 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M board_enable.c M chipset_enable.c M flashrom.c M include/programmer.h M internal.c 5 files changed, 69 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/56/73456/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/73456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I459215253845c2af73262943ce91a36464e9eb06 Gerrit-Change-Number: 73456 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in flashrom[master]: doc: Add build instructions
by Peter Marheine (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Thomas Heijligen, Stefan Reinauer, Anastasia Klimchuk. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/73359 ) Change subject: doc: Add build instructions ...................................................................... Patch Set 3: (1 comment) File doc/developers_doc/building_from_source.rst: https://review.coreboot.org/c/flashrom/+/73359/comment/218e1cf7_861729a0 PS3, Line 175: .. todo:: Write a sphinx extension to render ``meson_options.txt`` here `meson configure` will print out all options including project-specific ones, and the inline documentation for options isn't very useful right now (it doesn't seem useful unless you already have some idea of what the options do). I think the important options should either be documented manually here (providing more context for those that are typically interesting), or document that `meson configure` will show them (assuming that the plain information you get from there isn't very useful and it's not worth much effort to provide it inline here). -- To view, visit https://review.coreboot.org/c/flashrom/+/73359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I96771e98b313a6d26dd2be940ff37998d4124324 Gerrit-Change-Number: 73359 Gerrit-PatchSet: 3 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Mar 2023 02:04:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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