- flashrom-gerrit - mail.coreboot.org

[M] Change in flashrom[master]: flashchips: Add Macronix MX25V8035F support
by PoroCYon (Code Review) 20 Mar '23

20 Mar '23

PoroCYon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/73823 ) Change subject: flashchips: Add Macronix MX25V8035F support ...................................................................... flashchips: Add Macronix MX25V8035F support See https://www.macronix.com/Lists/Datasheet/Attachments/8405/MX25V8035F,%202.5… . I've only tested this patch with the MX25V1635F I have here, though other chips in the series exist as well. Tested using serprog and ftdi by writing a few images to the flash and seeing if changes were stored correctly. Change-Id: Ic5be2da4cfa2a2ff044a519bb6f367f21c15e4b8 Signed-off-by: PoroCYon <p(a)pcy.be> --- M flashchips.c M include/flashchips.h 2 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/23/73823/1 diff --git a/flashchips.c b/flashchips.c index 745cee5..ad0dbad 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9609,6 +9609,41 @@ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2300, 3600}, }, + { + .vendor = "Macronix", + .name = "MX25V8035F", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25V8035F, + .total_size = 1024, + .page_size = 256, + /* OTP: 8KiB total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_SCUR, + .tested = TEST_UNTESTED, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 4 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2300, 3600}, + }, { .vendor = "Macronix", diff --git a/include/flashchips.h b/include/flashchips.h index 58a6d0e..70ed544 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -513,6 +513,7 @@ #define MACRONIX_MX66L51235F 0x201a /* MX66L51235F, MX25L51245G */ #define MACRONIX_MX66L1G45G 0x201b /* MX66L1G45G */ #define MACRONIX_MX25V4035F 0x2313 +#define MACRONIX_MX25V8035F 0x2314 #define MACRONIX_MX25U8032E 0x2534 #define MACRONIX_MX25U1635E 0x2535 #define MACRONIX_MX25U3235E 0x2536 /* Same as MX25U6435F */ -- To view, visit https://review.coreboot.org/c/flashrom/+/73823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic5be2da4cfa2a2ff044a519bb6f367f21c15e4b8 Gerrit-Change-Number: 73823 Gerrit-PatchSet: 1 Gerrit-Owner: PoroCYon <p(a)pcy.be> Gerrit-MessageType: newchange

1 0

[M] Change in flashrom[master]: flashchips: Add Macronix MX25V1635F support
by PoroCYon (Code Review) 20 Mar '23

20 Mar '23

PoroCYon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/73824 ) Change subject: flashchips: Add Macronix MX25V1635F support ...................................................................... flashchips: Add Macronix MX25V1635F support See https://www.mxic.com.tw/Lists/Datasheet/Attachments/8662/MX25V1635F,%202.5V… . I've tested this patch with the MX25V1635F I have here, using serprog and ftdi by writing a few images to the flash and seeing if changes were stored correctly. Change-Id: I58ddaaa96ef410d50dde3aaa20376c5bbf0f370b Signed-off-by: PoroCYon <p(a)pcy.be> --- M flashchips.c M include/flashchips.h 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/73824/1 diff --git a/flashchips.c b/flashchips.c index ad0dbad..dc6e882 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9644,6 +9644,41 @@ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2300, 3600}, }, + { + .vendor = "Macronix", + .name = "MX25V1635F", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25V1635F, + .total_size = 2048, + .page_size = 256, + /* OTP: 8KiB total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_SCUR, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 4 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2300, 3600}, + }, { .vendor = "Macronix", diff --git a/include/flashchips.h b/include/flashchips.h index 70ed544..aa59a6d 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -514,6 +514,7 @@ #define MACRONIX_MX66L1G45G 0x201b /* MX66L1G45G */ #define MACRONIX_MX25V4035F 0x2313 #define MACRONIX_MX25V8035F 0x2314 +#define MACRONIX_MX25V1635F 0x2315 /* MX25V1636E */ #define MACRONIX_MX25U8032E 0x2534 #define MACRONIX_MX25U1635E 0x2535 #define MACRONIX_MX25U3235E 0x2536 /* Same as MX25U6435F */ -- To view, visit https://review.coreboot.org/c/flashrom/+/73824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I58ddaaa96ef410d50dde3aaa20376c5bbf0f370b Gerrit-Change-Number: 73824 Gerrit-PatchSet: 1 Gerrit-Owner: PoroCYon <p(a)pcy.be> Gerrit-MessageType: newchange

1 0

[M] Change in flashrom[master]: flashchips: Add Macronix MX25V4035F support
by PoroCYon (Code Review) 20 Mar '23

20 Mar '23

Attention is currently required from: PoroCYon, Angel Pons, Anastasia Klimchuk. Hello build bot (Jenkins), Thomas Heijligen, Angel Pons, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/73582 to look at the new patch set (#2). Change subject: flashchips: Add Macronix MX25V4035F support ...................................................................... flashchips: Add Macronix MX25V4035F support See https://www.macronix.com/Lists/Datasheet/Attachments/8670/MX25V4035F,%202.5… . I've only tested this patch with the MX25V1635F I have here, though other chips in the series exist as well. Tested using serprog and ftdi by writing a few images to the flash and seeing if changes were stored correctly. Change-Id: I8b26926c354b840ca7b14b4c5cb000e3c02f5137 Signed-off-by: PoroCYon <p(a)pcy.be> --- M flashchips.c M include/flashchips.h 2 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/82/73582/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/73582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8b26926c354b840ca7b14b4c5cb000e3c02f5137 Gerrit-Change-Number: 73582 Gerrit-PatchSet: 2 Gerrit-Owner: PoroCYon <p(a)pcy.be> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: PoroCYon <p(a)pcy.be> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

[M] Change in flashrom[master]: doc: Add contact page
by Thomas Heijligen (Code Review) 20 Mar '23

20 Mar '23

Thomas Heijligen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/flashrom/+/73822 ) Change subject: doc: Add contact page ...................................................................... doc: Add contact page This is just a copy of https://www.flashrom.org/Contact. Change-Id: Ibfba6a59c5a945b4238d16e07a07584f94159568 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- A doc/contact.rst M doc/index.rst 2 files changed, 155 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/22/73822/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/73822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ibfba6a59c5a945b4238d16e07a07584f94159568 Gerrit-Change-Number: 73822 Gerrit-PatchSet: 2 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newpatchset

1 0

[M] Change in flashrom[master]: doc: Add contact page
by Thomas Heijligen (Code Review) 20 Mar '23

20 Mar '23

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/73822 ) Change subject: doc: Add contact page ...................................................................... doc: Add contact page This is just a copy of https://www.flashrom.org/Contact. Change-Id: Ibfba6a59c5a945b4238d16e07a07584f94159568 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- A doc/contact.rst M doc/index.rst 2 files changed, 155 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/22/73822/1 diff --git a/doc/contact.rst b/doc/contact.rst new file mode 100644 index 0000000..40cac20 --- /dev/null +++ b/doc/contact.rst @@ -0,0 +1,142 @@ +Contact +======== +.. The extra = is needed to prevent git from throwing a `leftover conflict marker` + error when commiting. + +Mailing List +------------ +Flashrom related mails are welcome on the flashrom mailing list at `flashrom(a)flashrom.org <mailto:flashrom@flashrom.org>`_. +Please do NOT send any BIOS images or F segment dumps to the list! + +E-mails with binary files attached will be rejected. Images for things such as scope or logic analyzer traces are acceptable +if hosted on a third-party photo sharing service that assigns a unique URL to the image, such as Google Photos. +This prevents the photo URL from being abused for malicious or inappropriate content. + +Please note that the list is moderated for non-subscribers and we recommend to subscribe first. + +Subscription +"""""""""""" +https://mail.coreboot.org/postorius/lists/flashrom.flashrom.org/ + +Archives +"""""""" +https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/ +https://www.flashrom.org/pipermail/flashrom/ (Up to Dec. 2018) +https://marc.info/?l=flashrom +https://www.mail-archive.com/flashrom@flashrom.org/ + +Moderation rules +"""""""""""""""" +If your mail is too big (the current limit is 256 kB) or if you're not on the subscriber list, your mail will be held for moderation. +If your mail contains any BIOS images or F segment dumps (instead of links which are fine), the mail will be rejected for legal reasons +(we do not have the right to distribute BIOS images). + +IRC +--- +Some of the flashrom developers and users hang out in the `#flashrom <irc://irc.libera.chat/#flashrom>`_ +channel on the `Libera.chat <https://www.libera.chat/>`_ `IRC <https://en.wikipedia.org/wiki/Internet_Relay_Chat>`_ network. +If you don't have an IRC client, you can use the Libera.chat `webchat <https://web.libera.chat/#flashrom>`_. + +**#flashrom** channel is bridged to `Matrix <https://matrix.org/>`_. +If you would like to join, you can use `this invite link <https://matrix.to/#/#flashrom:libera.chat>`_. + +Here you have the chance to talk to people being involved or interested in this project. +Most of the discussion is tech talk and user help. + +Do note that IRC's nature has a significant effect on conversations. People from all over the world can join this channel +with many different cultures and timezones. Most people are in the `CET timezone <https://en.wikipedia.org/wiki/Central_European_Time>`_, +so the channel may be very quiet during `CET nighttime <https://time.is/CET>`_. + +If you have a problem and would like to get help, don't ask for help. Instead, just **explain** your problem right away, +and make sure to **describe** the situation as much as possible, so that other people can understand you and provide meaningful answers. +Otherwise, others have to ask or guess the details of your problem, which is frustrating for both parties. + +If you receive no replies, **please be patient**. +After all, silence is better than getting replied with `"IDK" <https://en.wiktionary.org/wiki/IDK>`_. +Frequently, somebody knows the answer, but hasn't checked IRC yet. In any case, please **do not leave the channel while waiting for an answer!** +Since IRC does not store messages, replying to somebody who left the channel is **impossible**. + +To have persistence on IRC, you can set up an `IRC bouncer <https://en.wikipedia.org/wiki/Internet_Relay_Chat#Bouncer>`_ +like `ZNC <https://en.wikipedia.org/wiki/ZNC>`_, or use `IRCCloud <https://www.irccloud.com/>`_. +Please **do not publish any logs** of this channel. + +Most of the time, people use IRC on wider-than-tall screens. Because of this, consider that pressing the return key is expensive. +Instead of sending lots of tiny messages with only about two words, prefer using longer sentences, spaces and punctuation symbols. +If reading and understanding your messages is easy, replying to them is also easy. + +Should you need to paste lots of text (more than three lines), please use a `paste service <https://en.wikipedia.org/wiki/Pastebin>`_. +For flashrom logs, feel free to use `paste.flashrom.org <https://paste.flashrom.org>`_. +Other good paste services are `ix.io <http://ix.io/>`_, `paste.rs <https://paste.rs/>`_, `bpaste.net <https://bpaste.net/>`_, +`gist.github.com <https://gist.github.com/>`_ and `dpaste.com <http://dpaste.com/>`_. + +Questions on `coreboot <https://coreboot.org>`_, `OpenBIOS <http://www.openbios.info/>`_, firmware and related topics are welcome in **#coreboot** on the same server. + +Dev meeting +----------- +Flashrom developers community runs an online meeting every two weeks. +The main purpose of the meeting is to discuss development plans, ideas, +current ongoing projects, pending patches, and sometimes organisational questions. + +Note this meeting is NOT: + +* troubleshooting session +* tech support forum +* user training session +* For questions above, please use IRC or the mailing list. + +Time of meeting +""""""""""""""" +It runs once every two weeks. + +**IMPORTANT**: please calculate meeting time for your local timezone. + +Between November and March (inclusive) + + **Wednesday 21:00-22:00 UTC+0** + + also known as + + | Wednesday 13.00-14.00 Pacific Standard Time UTC-8 + | Wednesday 22.00-23.00 Central European Time UTC+1 + | Thursday 8.00-9.00am Australian Eastern Daylight Time UTC+11 + +Between April and September (inclusive) + + **Thursday 6.00-7.00am UTC+0** + + also known as + + | Wednesday 11pm-midnight Pacific Daylight Time UTC-7 + | Thursday 8.00-9.00am Central European Summer Time UTC+2 + | Thursday 16.00-17.00 Australian Eastern Standard Time UTC+10 + +The last week of March and 4 weeks of October there are no meetings +This is because daylight saving time changes are happening on different dates in different locations, and setting up meeting time becomes too complicated. + +FAQ +--- +**When is the next meeting?** + +Look into the meeting notes `document <https://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZkADzQSH6WF…>`_. +The top entry, on the first page, with the date in the future, and empty list of attendees - is the next meeting. + + +**How to join the meeting?** + +In the meeting notes `document <https://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZkADzQSH6WF…>`_, +on the top it says “to join, click the link”, click the link. + + +**Do I need an invitation to join the meeting?** + +No, just join. + + +**Do I need to create an account anywhere?** + +No, you can join without an account, and view/comment on the meeting doc without an account. + + +**How do I add a topic to the agenda?** + +Add comments/suggestions on the meeting doc, and they will be accepted shortly after. diff --git a/doc/index.rst b/doc/index.rst index 3a83630..ea1027e 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -8,5 +8,6 @@ dev_guide/index classic_cli_manpage + contact .. include:: ../README -- To view, visit https://review.coreboot.org/c/flashrom/+/73822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ibfba6a59c5a945b4238d16e07a07584f94159568 Gerrit-Change-Number: 73822 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

1 0

[L] Change in flashrom[master]: cli_classic: include a fallback inplementation of getopt
by Thomas Heijligen (Code Review) 20 Mar '23

20 Mar '23

Attention is currently required from: Thomas Heijligen, Edward O'Callaghan, Angel Pons. Hello build bot (Jenkins), Edward O'Callaghan, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/73102 to look at the new patch set (#8). Change subject: cli_classic: include a fallback inplementation of getopt ...................................................................... cli_classic: include a fallback inplementation of getopt Some systems, DJGPP/DOS for now, may not provide getopt and their gnu extensions. So provide a fallback implementation. The code is based on musl libc. Change-Id: I6ebbde075014e3b45b0f9e04b34b72aa969e1197 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M cli_classic.c A cli_getopt.c A include/cli_classic.h M meson.build 4 files changed, 338 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/02/73102/8 -- To view, visit https://review.coreboot.org/c/flashrom/+/73102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6ebbde075014e3b45b0f9e04b34b72aa969e1197 Gerrit-Change-Number: 73102 Gerrit-PatchSet: 8 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in flashrom[master]: flashchips: Add Macronix MX25Vxx35F support
by Thomas Heijligen (Code Review) 20 Mar '23

20 Mar '23

Attention is currently required from: PoroCYon, Angel Pons, Anastasia Klimchuk. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/73582 ) Change subject: flashchips: Add Macronix MX25Vxx35F support ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: Seems good, only minor things. Can you split the patch into three to have one for each new flashchip. Also adding a link to the corresponding datasheets in the commit message. File flashchips.c: https://review.coreboot.org/c/flashrom/+/73582/comment/1e58ce5f_639d6e87 PS1, Line 9671: { : .eraseblocks = { {2 * 1024 * 1024, 1} }, : .block_erase = SPI_BLOCK_ERASE_60, : } The chip erase can also be performed with `SPI_BLOCK_ERASE_C7` Page 49, Figure 29 in the datasheet. -- To view, visit https://review.coreboot.org/c/flashrom/+/73582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8b26926c354b840ca7b14b4c5cb000e3c02f5137 Gerrit-Change-Number: 73582 Gerrit-PatchSet: 1 Gerrit-Owner: PoroCYon <p(a)pcy.be> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: PoroCYon <p(a)pcy.be> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 20 Mar 2023 11:36:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in flashrom[master]: tree/: Convert printlock func ptr into enumerate values
by Sam McNally (Code Review) 20 Mar '23

20 Mar '23

Attention is currently required from: Edward O'Callaghan. Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69934 ) Change subject: tree/: Convert printlock func ptr into enumerate values ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/69934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9131348f72c1010e2c213dca4dc4b675a8d8681e Gerrit-Change-Number: 69934 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Mon, 20 Mar 2023 04:44:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in flashrom[master]: tree/: Convert printlock func ptr into enumerate values
by Edward O'Callaghan (Code Review) 20 Mar '23

20 Mar '23

Attention is currently required from: Liam Flaherty. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69934 ) Change subject: tree/: Convert printlock func ptr into enumerate values ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/flashrom/+/69934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9131348f72c1010e2c213dca4dc4b675a8d8681e Gerrit-Change-Number: 69934 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Comment-Date: Mon, 20 Mar 2023 03:07:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in flashrom[master]: tree/: Convert unlock func ptr into enumerate values
by Edward O'Callaghan (Code Review) 20 Mar '23

20 Mar '23

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/69933 ) Change subject: tree/: Convert unlock func ptr into enumerate values ...................................................................... tree/: Convert unlock func ptr into enumerate values Converting the blockprotect unlock function pointer within the flashchip struct into enum values allows for the flashchips db to be turn into pure, declarative data. A nice side-effect of this is to reduce link-time symbol space of chipdrivers and increase modularity of the spi25_statusreg.c and related implementations. BUG=none TEST=ninja test. Change-Id: Ie5c5db1b09d07e1a549990d6f5a622fae4c83233 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69933 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sam McNally <sammc(a)google.com> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M 82802ab.c M flashrom.c M include/chipdrivers.h M include/flash.h M printlock.c M spi25_statusreg.c M tests/chip.c M tests/chip_wp.c 8 files changed, 154 insertions(+), 74 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/82802ab.c b/82802ab.c index 90c9cf0..a440bd4 100644 --- a/82802ab.c +++ b/82802ab.c @@ -142,7 +142,7 @@ return 0; } -int unlock_28f004s5(struct flashctx *flash) +static int unlock_28f004s5(struct flashctx *flash) { chipaddr bios = flash->virtual_memory; uint8_t mcfg, bcfg; @@ -195,7 +195,7 @@ return 0; } -int unlock_lh28f008bjt(struct flashctx *flash) +static int unlock_lh28f008bjt(struct flashctx *flash) { chipaddr bios = flash->virtual_memory; uint8_t mcfg, bcfg; @@ -249,3 +249,12 @@ return 0; } + +blockprotect_func_t *lookup_82802ab_blockprotect_func_ptr(const struct flashchip *const chip) +{ + switch (chip->unlock) { + case UNLOCK_28F004S5: return unlock_28f004s5; + case UNLOCK_LH28F008BJT: return unlock_lh28f008bjt; + default: return NULL; /* fallthough */ + }; +} diff --git a/flashrom.c b/flashrom.c index 3cf67f1..c5b795c 100644 --- a/flashrom.c +++ b/flashrom.c @@ -2080,9 +2080,9 @@ if (ret) msg_cerr("Failed to unlock flash status reg with wp support.\n"); } - if (ret && flash->chip->unlock) { - flash->chip->unlock(flash); - } + blockprotect_func_t *bp_func = lookup_blockprotect_func_ptr(flash->chip); + if (ret && bp_func) + bp_func(flash); flash->address_high_byte = -1; flash->in_4ba_mode = false; diff --git a/include/chipdrivers.h b/include/chipdrivers.h index c485aaf..bac7785 100644 --- a/include/chipdrivers.h +++ b/include/chipdrivers.h @@ -76,11 +76,6 @@ int spi_prettyprint_status_register_bp4_srwd(struct flashctx *flash); int spi_prettyprint_status_register_bp2_bpl(struct flashctx *flash); int spi_prettyprint_status_register_bp2_tb_bpl(struct flashctx *flash); -int spi_disable_blockprotect(struct flashctx *flash); -int spi_disable_blockprotect_bp1_srwd(struct flashctx *flash); -int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash); -int spi_disable_blockprotect_bp3_srwd(struct flashctx *flash); -int spi_disable_blockprotect_bp4_srwd(struct flashctx *flash); int spi_prettyprint_status_register_amic_a25l032(struct flashctx *flash); int spi_prettyprint_status_register_at25df(struct flashctx *flash); int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash); @@ -91,22 +86,12 @@ int spi_prettyprint_status_register_at25fs010(struct flashctx *flash); int spi_prettyprint_status_register_at25fs040(struct flashctx *flash); int spi_prettyprint_status_register_at26df081a(struct flashctx *flash); -int spi_disable_blockprotect_at2x_global_unprotect(struct flashctx *flash); -int spi_disable_blockprotect_at2x_global_unprotect_sec(struct flashctx *flash); -int spi_disable_blockprotect_at25f(struct flashctx *flash); -int spi_disable_blockprotect_at25f512a(struct flashctx *flash); -int spi_disable_blockprotect_at25f512b(struct flashctx *flash); -int spi_disable_blockprotect_at25fs010(struct flashctx *flash); -int spi_disable_blockprotect_at25fs040(struct flashctx *flash); int spi_prettyprint_status_register_en25s_wp(struct flashctx *flash); int spi_prettyprint_status_register_n25q(struct flashctx *flash); -int spi_disable_blockprotect_n25q(struct flashctx *flash); int spi_prettyprint_status_register_bp2_ep_srwd(struct flashctx *flash); -int spi_disable_blockprotect_bp2_ep_srwd(struct flashctx *flash); int spi_prettyprint_status_register_sst25(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf016(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf040b(struct flashctx *flash); -int spi_disable_blockprotect_sst26_global_unprotect(struct flashctx *flash); /* sfdp.c */ int probe_spi_sfdp(struct flashctx *flash); @@ -136,8 +121,7 @@ int erase_block_82802ab(struct flashctx *flash, unsigned int page, unsigned int pagesize); int write_82802ab(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); void print_status_82802ab(uint8_t status); -int unlock_28f004s5(struct flashctx *flash); -int unlock_lh28f008bjt(struct flashctx *flash); +blockprotect_func_t *lookup_82802ab_blockprotect_func_ptr(const struct flashchip *const chip); /* jedec.c */ uint8_t oddparity(uint8_t val); @@ -151,10 +135,7 @@ int erase_block_jedec(struct flashctx *flash, unsigned int page, unsigned int blocksize); int erase_chip_block_jedec(struct flashctx *flash, unsigned int page, unsigned int blocksize); -int unlock_regspace2_uniform_32k(struct flashctx *flash); -int unlock_regspace2_uniform_64k(struct flashctx *flash); -int unlock_regspace2_block_eraser_0(struct flashctx *flash); -int unlock_regspace2_block_eraser_1(struct flashctx *flash); +blockprotect_func_t *lookup_jedec_blockprotect_func_ptr(const struct flashchip *const chip); int printlock_regspace2_uniform_64k(struct flashctx *flash); int printlock_regspace2_block_eraser_0(struct flashctx *flash); int printlock_regspace2_block_eraser_1(struct flashctx *flash); diff --git a/include/flash.h b/include/flash.h index 3db38d2..10c2975 100644 --- a/include/flash.h +++ b/include/flash.h @@ -322,31 +322,34 @@ TEST_ERASE_INJECTOR, /* special case must come last. */ }; -#define NO_BLOCKPROTECT_FUNC NULL -#define SPI_DISABLE_BLOCKPROTECT spi_disable_blockprotect -#define SPI_DISABLE_BLOCKPROTECT_BP2_EP_SRWD spi_disable_blockprotect_bp2_ep_srwd -#define SPI_DISABLE_BLOCKPROTECT_BP1_SRWD spi_disable_blockprotect_bp1_srwd -#define SPI_DISABLE_BLOCKPROTECT_BP2_SRWD spi_disable_blockprotect_bp2_srwd -#define SPI_DISABLE_BLOCKPROTECT_BP3_SRWD spi_disable_blockprotect_bp3_srwd -#define SPI_DISABLE_BLOCKPROTECT_BP4_SRWD spi_disable_blockprotect_bp4_srwd -#define SPI_DISABLE_BLOCKPROTECT_AT45DB spi_disable_blockprotect_at45db -#define SPI_DISABLE_BLOCKPROTECT_AT25F spi_disable_blockprotect_at25f -#define SPI_DISABLE_BLOCKPROTECT_AT25FS010 spi_disable_blockprotect_at25fs010 -#define SPI_DISABLE_BLOCKPROTECT_AT25FS040 spi_disable_blockprotect_at25fs040 -#define SPI_DISABLE_BLOCKPROTECT_AT25F512A spi_disable_blockprotect_at25f512a -#define SPI_DISABLE_BLOCKPROTECT_AT25F512B spi_disable_blockprotect_at25f512b -#define SPI_DISABLE_BLOCKPROTECT_AT2X_GLOBAL_UNPROTECT spi_disable_blockprotect_at2x_global_unprotect -#define SPI_DISABLE_BLOCKPROTECT_AT2X_GLOBAL_UNPROTECT_SEC spi_disable_blockprotect_at2x_global_unprotect_sec -#define SPI_DISABLE_BLOCKPROTECT_SST26_GLOBAL_UNPROTECT spi_disable_blockprotect_sst26_global_unprotect -#define SPI_DISABLE_BLOCKPROTECT_N25Q spi_disable_blockprotect_n25q -#define UNLOCK_REGSPACE2_BLOCK_ERASER_0 unlock_regspace2_block_eraser_0 -#define UNLOCK_REGSPACE2_BLOCK_ERASER_1 unlock_regspace2_block_eraser_1 -#define UNLOCK_REGSPACE2_UNIFORM_32K unlock_regspace2_uniform_32k -#define UNLOCK_REGSPACE2_UNIFORM_64K unlock_regspace2_uniform_64k -#define UNLOCK_28F004S5 unlock_28f004s5 -#define UNLOCK_LH28F008BJT unlock_lh28f008bjt -#define UNLOCK_SST_FWHUB unlock_sst_fwhub -#define UNPROTECT_28SF040 unprotect_28sf040 +enum blockprotect_func { + NO_BLOCKPROTECT_FUNC = 0, /* 0 indicates no unlock function set. */ + SPI_DISABLE_BLOCKPROTECT, + SPI_DISABLE_BLOCKPROTECT_BP2_EP_SRWD, + SPI_DISABLE_BLOCKPROTECT_BP1_SRWD, + SPI_DISABLE_BLOCKPROTECT_BP2_SRWD, + SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, + SPI_DISABLE_BLOCKPROTECT_AT45DB, + SPI_DISABLE_BLOCKPROTECT_AT25F, + SPI_DISABLE_BLOCKPROTECT_AT25FS010, + SPI_DISABLE_BLOCKPROTECT_AT25FS040, + SPI_DISABLE_BLOCKPROTECT_AT25F512A, + SPI_DISABLE_BLOCKPROTECT_AT25F512B, + SPI_DISABLE_BLOCKPROTECT_AT2X_GLOBAL_UNPROTECT, + SPI_DISABLE_BLOCKPROTECT_AT2X_GLOBAL_UNPROTECT_SEC, + SPI_DISABLE_BLOCKPROTECT_SST26_GLOBAL_UNPROTECT, + SPI_DISABLE_BLOCKPROTECT_N25Q, + UNLOCK_REGSPACE2_BLOCK_ERASER_0, + UNLOCK_REGSPACE2_BLOCK_ERASER_1, + UNLOCK_REGSPACE2_UNIFORM_32K, + UNLOCK_REGSPACE2_UNIFORM_64K, + UNLOCK_28F004S5, + UNLOCK_LH28F008BJT, + UNLOCK_SST_FWHUB, + UNPROTECT_28SF040, + TEST_UNLOCK_INJECTOR, /* special case must come last. */ +}; #define NO_PRINTLOCK_FUNC NULL #define PRINTLOCK_AT49F printlock_at49f @@ -458,7 +461,7 @@ } block_erasers[NUM_ERASEFUNCTIONS]; int (*printlock) (struct flashctx *flash); - int (*unlock) (struct flashctx *flash); + enum blockprotect_func unlock; enum write_func write; enum read_func read; struct voltage { @@ -510,6 +513,8 @@ }; typedef int (*chip_restore_fn_cb_t)(struct flashctx *flash, void *data); +typedef int (blockprotect_func_t)(struct flashctx *flash); +blockprotect_func_t *lookup_blockprotect_func_ptr(const struct flashchip *const chip); struct flashrom_flashctx { struct flashchip *chip; diff --git a/printlock.c b/printlock.c index d05251e..f6eea7f 100644 --- a/printlock.c +++ b/printlock.c @@ -186,17 +186,17 @@ return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block_generic); } -int unlock_regspace2_uniform_64k(struct flashctx *flash) +static int unlock_regspace2_uniform_64k(struct flashctx *flash) { return unlock_regspace2_uniform(flash, 64 * 1024); } -int unlock_regspace2_uniform_32k(struct flashctx *flash) +static int unlock_regspace2_uniform_32k(struct flashctx *flash) { return unlock_regspace2_uniform(flash, 32 * 1024); } -int unlock_regspace2_block_eraser_0(struct flashctx *flash) +static int unlock_regspace2_block_eraser_0(struct flashctx *flash) { // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = @@ -204,10 +204,21 @@ return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } -int unlock_regspace2_block_eraser_1(struct flashctx *flash) +static int unlock_regspace2_block_eraser_1(struct flashctx *flash) { // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } + +blockprotect_func_t *lookup_jedec_blockprotect_func_ptr(const struct flashchip *const chip) +{ + switch (chip->unlock) { + case UNLOCK_REGSPACE2_BLOCK_ERASER_0: return unlock_regspace2_block_eraser_0; + case UNLOCK_REGSPACE2_BLOCK_ERASER_1: return unlock_regspace2_block_eraser_1; + case UNLOCK_REGSPACE2_UNIFORM_32K: return unlock_regspace2_uniform_32k; + case UNLOCK_REGSPACE2_UNIFORM_64K: return unlock_regspace2_uniform_64k; + default: return NULL; /* fallthough */ + }; +} diff --git a/spi25_statusreg.c b/spi25_statusreg.c index d452416..21a1a15 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -363,12 +363,12 @@ } /* A common block protection disable that tries to unset the status register bits masked by 0x3C. */ -int spi_disable_blockprotect(struct flashctx *flash) +static int spi_disable_blockprotect(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x3C, 0, 0, 0xFF); } -int spi_disable_blockprotect_sst26_global_unprotect(struct flashctx *flash) +static int spi_disable_blockprotect_sst26_global_unprotect(struct flashctx *flash) { int result = spi_write_enable(flash); if (result) @@ -383,7 +383,7 @@ /* A common block protection disable that tries to unset the status register bits masked by 0x0C (BP0-1) and * protected/locked by bit #7. Useful when bits 4-5 may be non-0). */ -int spi_disable_blockprotect_bp1_srwd(struct flashctx *flash) +static int spi_disable_blockprotect_bp1_srwd(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 0, 0xFF); } @@ -391,21 +391,21 @@ /* A common block protection disable that tries to unset the status register bits masked by 0x1C (BP0-2) and * protected/locked by bit #7. Useful when bit #5 is neither a protection bit nor reserved (and hence possibly * non-0). */ -int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash) +static int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0, 0xFF); } /* A common block protection disable that tries to unset the status register bits masked by 0x3C (BP0-3) and * protected/locked by bit #7. */ -int spi_disable_blockprotect_bp3_srwd(struct flashctx *flash) +static int spi_disable_blockprotect_bp3_srwd(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x3C, 1 << 7, 0, 0xFF); } /* A common block protection disable that tries to unset the status register bits masked by 0x7C (BP0-4) and * protected/locked by bit #7. */ -int spi_disable_blockprotect_bp4_srwd(struct flashctx *flash) +static int spi_disable_blockprotect_bp4_srwd(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF); } @@ -825,39 +825,39 @@ * sectors at once by writing 0 not only the protection bits (2 and 3) but also completely unrelated bits (4 and * 5) which normally are not touched. * Affected are all known Atmel chips matched by AT2[56]D[FLQ]..1A? but the AT26DF041. */ -int spi_disable_blockprotect_at2x_global_unprotect(struct flashctx *flash) +static int spi_disable_blockprotect_at2x_global_unprotect(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 1 << 4, 0x00); } -int spi_disable_blockprotect_at2x_global_unprotect_sec(struct flashctx *flash) +static int spi_disable_blockprotect_at2x_global_unprotect_sec(struct flashctx *flash) { /* FIXME: We should check the security lockdown. */ msg_cinfo("Ignoring security lockdown (if present)\n"); return spi_disable_blockprotect_at2x_global_unprotect(flash); } -int spi_disable_blockprotect_at25f(struct flashctx *flash) +static int spi_disable_blockprotect_at25f(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 0, 0xFF); } -int spi_disable_blockprotect_at25f512a(struct flashctx *flash) +static int spi_disable_blockprotect_at25f512a(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x04, 1 << 7, 0, 0xFF); } -int spi_disable_blockprotect_at25f512b(struct flashctx *flash) +static int spi_disable_blockprotect_at25f512b(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x04, 1 << 7, 1 << 4, 0xFF); } -int spi_disable_blockprotect_at25fs010(struct flashctx *flash) +static int spi_disable_blockprotect_at25fs010(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x6C, 1 << 7, 0, 0xFF); } -int spi_disable_blockprotect_at25fs040(struct flashctx *flash) +static int spi_disable_blockprotect_at25fs040(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF); } @@ -881,7 +881,7 @@ /* === Intel/Numonyx/Micron - Spansion === */ -int spi_disable_blockprotect_n25q(struct flashctx *flash) +static int spi_disable_blockprotect_n25q(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x5C, 1 << 7, 0, 0xFF); } @@ -908,11 +908,56 @@ /* Used by Intel/Numonyx S33 and Spansion S25FL-S chips */ /* TODO: Clear P_FAIL and E_FAIL with Clear SR Fail Flags Command (30h) here? */ -int spi_disable_blockprotect_bp2_ep_srwd(struct flashctx *flash) +static int spi_disable_blockprotect_bp2_ep_srwd(struct flashctx *flash) { return spi_disable_blockprotect_bp2_srwd(flash); } +/* special unit-test hook */ +blockprotect_func_t *g_test_unlock_injector; + +blockprotect_func_t *lookup_blockprotect_func_ptr(const struct flashchip *const chip) +{ + switch (chip->unlock) { + case SPI_DISABLE_BLOCKPROTECT: return spi_disable_blockprotect; + case SPI_DISABLE_BLOCKPROTECT_BP2_EP_SRWD: return spi_disable_blockprotect_bp2_ep_srwd; + case SPI_DISABLE_BLOCKPROTECT_BP1_SRWD: return spi_disable_blockprotect_bp1_srwd; + case SPI_DISABLE_BLOCKPROTECT_BP2_SRWD: return spi_disable_blockprotect_bp2_srwd; + case SPI_DISABLE_BLOCKPROTECT_BP3_SRWD: return spi_disable_blockprotect_bp3_srwd; + case SPI_DISABLE_BLOCKPROTECT_BP4_SRWD: return spi_disable_blockprotect_bp4_srwd; + case SPI_DISABLE_BLOCKPROTECT_AT45DB: return spi_disable_blockprotect_at45db; /* at45db.c */ + case SPI_DISABLE_BLOCKPROTECT_AT25F: return spi_disable_blockprotect_at25f; + case SPI_DISABLE_BLOCKPROTECT_AT25FS010: return spi_disable_blockprotect_at25fs010; + case SPI_DISABLE_BLOCKPROTECT_AT25FS040: return spi_disable_blockprotect_at25fs040; + case SPI_DISABLE_BLOCKPROTECT_AT25F512A: return spi_disable_blockprotect_at25f512a; + case SPI_DISABLE_BLOCKPROTECT_AT25F512B: return spi_disable_blockprotect_at25f512b; + case SPI_DISABLE_BLOCKPROTECT_AT2X_GLOBAL_UNPROTECT: return spi_disable_blockprotect_at2x_global_unprotect; + case SPI_DISABLE_BLOCKPROTECT_AT2X_GLOBAL_UNPROTECT_SEC: return spi_disable_blockprotect_at2x_global_unprotect_sec; + case SPI_DISABLE_BLOCKPROTECT_SST26_GLOBAL_UNPROTECT: return spi_disable_blockprotect_sst26_global_unprotect; + case SPI_DISABLE_BLOCKPROTECT_N25Q: return spi_disable_blockprotect_n25q; + /* fallthough to lookup_jedec_blockprotect_func_ptr() */ + case UNLOCK_REGSPACE2_BLOCK_ERASER_0: + case UNLOCK_REGSPACE2_BLOCK_ERASER_1: + case UNLOCK_REGSPACE2_UNIFORM_32K: + case UNLOCK_REGSPACE2_UNIFORM_64K: + return lookup_jedec_blockprotect_func_ptr(chip); + /* fallthough to lookup_82802ab_blockprotect_func_ptr() */ + case UNLOCK_28F004S5: + case UNLOCK_LH28F008BJT: + return lookup_82802ab_blockprotect_func_ptr(chip); + case UNLOCK_SST_FWHUB: return unlock_sst_fwhub; /* sst_fwhub.c */ + case UNPROTECT_28SF040: return unprotect_28sf040; /* sst28sf040.c */ + case TEST_UNLOCK_INJECTOR: return g_test_unlock_injector; + /* default: non-total function, 0 indicates no unlock function set. + * We explicitly do not want a default catch-all case in the switch + * to ensure unhandled enum's are compiler warnings. + */ + case NO_BLOCKPROTECT_FUNC: return NULL; + }; + + return NULL; +} + /* Used by Intel/Numonyx S33 and Spansion S25FL-S chips */ int spi_prettyprint_status_register_bp2_ep_srwd(struct flashctx *flash) { diff --git a/tests/chip.c b/tests/chip.c index ad0d770..6a17d86 100644 --- a/tests/chip.c +++ b/tests/chip.c @@ -149,6 +149,7 @@ extern write_func_t *g_test_write_injector; extern read_func_t *g_test_read_injector; extern erasefunc_t *g_test_erase_injector; +extern blockprotect_func_t *g_test_unlock_injector; static const struct flashchip chip_8MiB = { .vendor = "aklm", @@ -156,7 +157,7 @@ .tested = TEST_OK_PREW, .read = TEST_READ_INJECTOR, .write = TEST_WRITE_INJECTOR, - .unlock = unlock_chip, + .unlock = TEST_UNLOCK_INJECTOR, .block_erasers = {{ /* All blocks within total size of the chip. */ @@ -172,7 +173,7 @@ .tested = TEST_OK_PREW, .read = SPI_CHIP_READ, .write = SPI_CHIP_WRITE256, - .unlock = spi_disable_blockprotect, + .unlock = SPI_DISABLE_BLOCKPROTECT, .page_size = 256, .block_erasers = { @@ -210,6 +211,7 @@ g_test_write_injector = write_chip; g_test_read_injector = read_chip; g_test_erase_injector = block_erase_chip; + g_test_unlock_injector = unlock_chip; struct flashrom_flashctx flashctx = { 0 }; struct flashrom_layout *layout; struct flashchip mock_chip = chip_8MiB; @@ -269,6 +271,7 @@ g_test_write_injector = write_chip; g_test_read_injector = read_chip; g_test_erase_injector = block_erase_chip; + g_test_unlock_injector = unlock_chip; struct flashrom_flashctx flashctx = { 0 }; struct flashrom_layout *layout; struct flashchip mock_chip = chip_8MiB; @@ -344,6 +347,7 @@ g_test_write_injector = write_chip; g_test_read_injector = read_chip; g_test_erase_injector = block_erase_chip; + g_test_unlock_injector = unlock_chip; struct flashrom_flashctx flashctx = { 0 }; struct flashrom_layout *layout; struct flashchip mock_chip = chip_8MiB; @@ -535,6 +539,7 @@ g_test_write_injector = write_chip; g_test_read_injector = read_chip; g_test_erase_injector = block_erase_chip; + g_test_unlock_injector = unlock_chip; struct flashrom_flashctx flashctx = { 0 }; struct flashrom_layout *layout; struct flashchip mock_chip = chip_8MiB; diff --git a/tests/chip_wp.c b/tests/chip_wp.c index 9607a96..2686f44 100644 --- a/tests/chip_wp.c +++ b/tests/chip_wp.c @@ -67,7 +67,7 @@ .tested = TEST_OK_PREW, .read = SPI_CHIP_READ, .write = SPI_CHIP_WRITE256, - .unlock = spi_disable_blockprotect, + .unlock = SPI_DISABLE_BLOCKPROTECT, .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_WRSR2 | FEATURE_WRSR3, .block_erasers = { -- To view, visit https://review.coreboot.org/c/flashrom/+/69933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie5c5db1b09d07e1a549990d6f5a622fae4c83233 Gerrit-Change-Number: 69933 Gerrit-PatchSet: 7 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

2024

2023

2022

2021

2020

2019

2018

2017

flashrom-gerrit