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Change in flashrom[master]: spi25: Integrate 4BA support
by Nico Huber (Code Review) 09 Nov '17

09 Nov '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22384 Change subject: spi25: Integrate 4BA support ...................................................................... spi25: Integrate 4BA support Allow 4-byte addresses for instructions usually used with 3-byte addresses. Decide in which way the 4th byte will be communicated based on the state of the chip (i.e. have we enabled 4BA mode) and a new feature bit for an extended address register. If we are not in 4BA mode and no extended address register is available or the write to it fails, bail out. We cache the state of 4BA mode and the extended address register in the flashctx. Change-Id: I644600beaab9a571b97b67f7516abe571d3460c1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M flash.h M flashrom.c M spi25.c M spi4ba.c M spi4ba.h 5 files changed, 53 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/84/22384/1 diff --git a/flash.h b/flash.h index b18d698..00b5962 100644 --- a/flash.h +++ b/flash.h @@ -120,6 +120,8 @@ #define FEATURE_OTP (1 << 8) #define FEATURE_QPI (1 << 9) #define FEATURE_4BA_SUPPORT (1 << 10) +#define FEATURE_4BA_EXT_ADDR (1 << 11) /**< Regular 3-byte operations can be used by writing the most + signifcant address byte into an extended address register. */ enum test_state { OK = 0, @@ -236,6 +238,8 @@ bool verify_after_write; bool verify_whole_chip; } flags; + int address_high_byte; + bool in_4ba_mode; }; /* Timing used in probe routines. ZERO is -2 to differentiate between an unset diff --git a/flashrom.c b/flashrom.c index 4fe1843..db133e6 100644 --- a/flashrom.c +++ b/flashrom.c @@ -2215,6 +2215,9 @@ if (flash->chip->unlock) flash->chip->unlock(flash); + flash->address_high_byte = -1; + flash->in_4ba_mode = false; + /* Enable/disable 4-byte addressing mode if flash chip supports it */ if ((flash->chip->feature_bits & FEATURE_4BA_SUPPORT) && flash->chip->four_bytes_addr_funcs.set_4ba) { diff --git a/spi25.c b/spi25.c index 5b14a99..e7fdaaf 100644 --- a/spi25.c +++ b/spi25.c @@ -363,14 +363,37 @@ return result ? result : status; } +static int spi_set_extended_address(struct flashctx *const flash, const uint8_t addr_high) +{ + if (flash->address_high_byte != addr_high && + spi_write_extended_address_register(flash, addr_high)) + return -1; + flash->address_high_byte = addr_high; + return 0; +} + static int spi_prepare_address(struct flashctx *const flash, uint8_t cmd_buf[], const unsigned int addr) { - /* TODO: extend for 4BA */ - cmd_buf[1] = (addr >> 16) & 0xff; - cmd_buf[2] = (addr >> 8) & 0xff; - cmd_buf[3] = (addr >> 0) & 0xff; - return 3; + if (flash->in_4ba_mode) { + cmd_buf[1] = (addr >> 24) & 0xff; + cmd_buf[2] = (addr >> 16) & 0xff; + cmd_buf[3] = (addr >> 8) & 0xff; + cmd_buf[4] = (addr >> 0) & 0xff; + return 4; + } else { + if (flash->chip->feature_bits & FEATURE_4BA_EXT_ADDR) { + if (spi_set_extended_address(flash, addr >> 24)) + return -1; + } else { + if (addr >> 24) + return -1; + } + cmd_buf[1] = (addr >> 16) & 0xff; + cmd_buf[2] = (addr >> 8) & 0xff; + cmd_buf[3] = (addr >> 0) & 0xff; + return 3; + } } /** diff --git a/spi4ba.c b/spi4ba.c index a44e067..902f073 100644 --- a/spi4ba.c +++ b/spi4ba.c @@ -39,12 +39,17 @@ /* Enter 4-bytes addressing mode (without sending WREN before) */ int spi_enter_4ba_b7(struct flashctx *flash) { + int result; const unsigned char cmd[JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE] = { JEDEC_ENTER_4_BYTE_ADDR_MODE }; msg_trace("-> %s\n", __func__); /* Switch to 4-bytes addressing mode */ - return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); + if (!result) + flash->in_4ba_mode = true; + + return result; } /* Enter 4-bytes addressing mode with sending WREN before */ @@ -75,18 +80,25 @@ result = spi_send_multicommand(flash, cmds); if (result) msg_cerr("%s failed during command execution\n", __func__); + else + flash->in_4ba_mode = true; return result; } /* Exit 4-bytes addressing mode (without sending WREN before) */ int spi_exit_4ba_e9(struct flashctx *flash) { + int result; const unsigned char cmd[JEDEC_EXIT_4_BYTE_ADDR_MODE_OUTSIZE] = { JEDEC_EXIT_4_BYTE_ADDR_MODE }; msg_trace("-> %s\n", __func__); /* Switch to 3-bytes addressing mode */ - return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); + if (!result) + flash->in_4ba_mode = false; + + return result; } /* Exit 4-bytes addressing mode with sending WREN before */ @@ -115,9 +127,10 @@ /* Switch to 3-bytes addressing mode */ result = spi_send_multicommand(flash, cmds); - if (result) { + if (result) msg_cerr("%s failed during command execution\n", __func__); - } + else + flash->in_4ba_mode = false; return result; } diff --git a/spi4ba.h b/spi4ba.h index 8a01792..a0316bc 100644 --- a/spi4ba.h +++ b/spi4ba.h @@ -114,5 +114,6 @@ int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_write_extended_address_register(struct flashctx *flash, uint8_t regdata); #endif /* __SPI_4BA_H__ */ -- To view, visit https://review.coreboot.org/22384 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I644600beaab9a571b97b67f7516abe571d3460c1 Gerrit-Change-Number: 22384 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[master]: spi25: Enable native 4BA read and write using feature bits
by Nico Huber (Code Review) 09 Nov '17

09 Nov '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22385 Change subject: spi25: Enable native 4BA read and write using feature bits ...................................................................... spi25: Enable native 4BA read and write using feature bits Prefer the native 4BA instruction when they are supported. In this case, override our logic to decide to use a 4BA address. Change-Id: I2f6817ca198bf923671a7aa67e956e5477d71848 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M flash.h M flashchips.c M spi25.c 3 files changed, 28 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/85/22385/1 diff --git a/flash.h b/flash.h index 00b5962..40c7f28 100644 --- a/flash.h +++ b/flash.h @@ -122,6 +122,8 @@ #define FEATURE_4BA_SUPPORT (1 << 10) #define FEATURE_4BA_EXT_ADDR (1 << 11) /**< Regular 3-byte operations can be used by writing the most signifcant address byte into an extended address register. */ +#define FEATURE_4BA_READ (1 << 12) /**< Native 4BA read instruction (0x13) is supported. */ +#define FEATURE_4BA_WRITE (1 << 13) /**< Native 4BA byte program (0x12) is supported. */ enum test_state { OK = 0, diff --git a/flashchips.c b/flashchips.c index a1ad445..05a2906 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9846,7 +9846,7 @@ .page_size = 256, /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT | FEATURE_4BA_READ | FEATURE_4BA_WRITE, .four_bytes_addr_funcs = { .read_nbyte = spi_nbyte_read_4ba_direct, @@ -9885,7 +9885,7 @@ .page_size = 256, /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT | FEATURE_4BA_READ | FEATURE_4BA_WRITE, .four_bytes_addr_funcs = { .read_nbyte = spi_nbyte_read_4ba_direct, @@ -14769,7 +14769,7 @@ /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT | FEATURE_4BA_READ, .four_bytes_addr_funcs = { .set_4ba = spi_enter_4ba_b7_we, /* enter 4-bytes addressing mode by CMD B7 + WREN */ diff --git a/spi25.c b/spi25.c index e7fdaaf..67a56df 100644 --- a/spi25.c +++ b/spi25.c @@ -24,6 +24,7 @@ #include <stddef.h> #include <string.h> +#include <stdbool.h> #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" @@ -372,10 +373,10 @@ return 0; } -static int spi_prepare_address(struct flashctx *const flash, - uint8_t cmd_buf[], const unsigned int addr) +static int spi_prepare_address(struct flashctx *const flash, uint8_t cmd_buf[], + const bool native_4ba, const unsigned int addr) { - if (flash->in_4ba_mode) { + if (native_4ba || flash->in_4ba_mode) { cmd_buf[1] = (addr >> 24) & 0xff; cmd_buf[2] = (addr >> 16) & 0xff; cmd_buf[3] = (addr >> 8) & 0xff; @@ -402,6 +403,7 @@ * * @param flash the flash chip's context * @param op the operation to execute + * @param native_4ba whether `op` always takes a 4-byte address * @param addr the address parameter to `op` * @param out_bytes bytes to send after the address, * may be NULL iff `out_bytes` is 0 @@ -409,8 +411,8 @@ * @param poll_delay interval in us for polling WIP * @return 0 on success, non-zero otherwise */ -static int spi_write_cmd(struct flashctx *const flash, - const uint8_t op, const unsigned int addr, +static int spi_write_cmd(struct flashctx *const flash, const uint8_t op, + const bool native_4ba, const unsigned int addr, const uint8_t *const out_bytes, const size_t out_len, const unsigned int poll_delay) { @@ -426,7 +428,7 @@ }; cmd[0] = op; - const int addr_len = spi_prepare_address(flash, cmd, addr); + const int addr_len = spi_prepare_address(flash, cmd, native_4ba, addr); if (addr_len < 0) return 1; @@ -469,7 +471,7 @@ unsigned int blocklen) { /* This usually takes 100-4000ms, so wait in 100ms steps. */ - return spi_write_cmd(flash, 0x52, addr, NULL, 0, 100 * 1000); + return spi_write_cmd(flash, 0x52, false, addr, NULL, 0, 100 * 1000); } /* Block size is usually @@ -478,7 +480,7 @@ int spi_block_erase_c4(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { /* This usually takes 240-480s, so wait in 500ms steps. */ - return spi_write_cmd(flash, 0xc4, addr, NULL, 0, 500 * 1000); + return spi_write_cmd(flash, 0xc4, false, addr, NULL, 0, 500 * 1000); } /* Block size is usually @@ -490,7 +492,7 @@ unsigned int blocklen) { /* This usually takes 100-4000ms, so wait in 100ms steps. */ - return spi_write_cmd(flash, 0xd8, addr, NULL, 0, 100 * 1000); + return spi_write_cmd(flash, 0xd8, false, addr, NULL, 0, 100 * 1000); } /* Block size is usually @@ -500,7 +502,7 @@ unsigned int blocklen) { /* This usually takes 100-4000ms, so wait in 100ms steps. */ - return spi_write_cmd(flash, 0xd7, addr, NULL, 0, 100 * 1000); + return spi_write_cmd(flash, 0xd7, false, addr, NULL, 0, 100 * 1000); } /* Page erase (usually 256B blocks) */ @@ -508,7 +510,7 @@ { /* This takes up to 20ms usually (on worn out devices up to the 0.5s range), so wait in 1ms steps. */ - return spi_write_cmd(flash, 0xdb, addr, NULL, 0, 1 * 1000); + return spi_write_cmd(flash, 0xdb, false, addr, NULL, 0, 1 * 1000); } /* Sector size is usually 4k, though Macronix eliteflash has 64k */ @@ -516,19 +518,19 @@ unsigned int blocklen) { /* This usually takes 15-800ms, so wait in 10ms steps. */ - return spi_write_cmd(flash, 0x20, addr, NULL, 0, 10 * 1000); + return spi_write_cmd(flash, 0x20, false, addr, NULL, 0, 10 * 1000); } int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { /* This usually takes 10ms, so wait in 1ms steps. */ - return spi_write_cmd(flash, 0x50, addr, NULL, 0, 1 * 1000); + return spi_write_cmd(flash, 0x50, false, addr, NULL, 0, 1 * 1000); } int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { /* This usually takes 8ms, so wait in 1ms steps. */ - return spi_write_cmd(flash, 0x81, addr, NULL, 0, 1 * 1000); + return spi_write_cmd(flash, 0x81, false, addr, NULL, 0, 1 * 1000); } int spi_block_erase_60(struct flashctx *flash, unsigned int addr, @@ -601,15 +603,18 @@ static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) { - return spi_write_cmd(flash, JEDEC_BYTE_PROGRAM, addr, bytes, len, 10); + const bool native_4ba = !!(flash->chip->feature_bits & FEATURE_4BA_WRITE); + const uint8_t op = native_4ba ? JEDEC_BYTE_PROGRAM_4BA : JEDEC_BYTE_PROGRAM; + return spi_write_cmd(flash, op, native_4ba, addr, bytes, len, 10); } int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes, unsigned int len) { - uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN] = { JEDEC_READ, }; + const bool native_4ba = !!(flash->chip->feature_bits & FEATURE_4BA_READ); + uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN] = { native_4ba ? JEDEC_READ_4BA : JEDEC_READ, }; - const int addr_len = spi_prepare_address(flash, cmd, address); + const int addr_len = spi_prepare_address(flash, cmd, native_4ba, address); if (addr_len < 0) return 1; @@ -781,7 +786,7 @@ //return SPI_GENERIC_ERROR; } - result = spi_write_cmd(flash, JEDEC_AAI_WORD_PROGRAM, start, buf + pos - start, 2, 10); + result = spi_write_cmd(flash, JEDEC_AAI_WORD_PROGRAM, false, start, buf + pos - start, 2, 10); if (result) goto bailout; -- To view, visit https://review.coreboot.org/22385 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2f6817ca198bf923671a7aa67e956e5477d71848 Gerrit-Change-Number: 22385 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[master]: spi25: Use common code for nbyte read/write and block erase
by Nico Huber (Code Review) 09 Nov '17

09 Nov '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22383 Change subject: spi25: Use common code for nbyte read/write and block erase ...................................................................... spi25: Use common code for nbyte read/write and block erase Introduce spi_prepare_address() and spi_write_cmd() and use them in nbyte_program, nbyte_read and block-erase procedures. The former abstracts over the address part of a SPI command to make it exten- sible for 4-byte adressing. spi_write_cmd() implements a WREN + write operation with address and optionally up to 256 bytes of data. It provides a common path to reduce overall redundancy. Also, reduce the polling delay in spi_block_erase_c4() from 500s to 500ms as the comment suggests. Change-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M chipdrivers.h M spi.h M spi25.c 3 files changed, 105 insertions(+), 429 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/22383/1 diff --git a/chipdrivers.h b/chipdrivers.h index 16a75a9..12fc5a3 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -55,8 +55,6 @@ int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); -int spi_byte_program(struct flashctx *flash, unsigned int addr, uint8_t databyte); -int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); int spi_nbyte_read(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); int spi_write_chunked(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); diff --git a/spi.h b/spi.h index de5b3be..41b0245 100644 --- a/spi.h +++ b/spi.h @@ -24,6 +24,8 @@ * Contains the generic SPI headers */ +#define JEDEC_MAX_ADDR_LEN 0x04 + /* Read Electronic ID */ #define JEDEC_RDID 0x9f #define JEDEC_RDID_OUTSIZE 0x01 diff --git a/spi25.c b/spi25.c index da04d2e..5b14a99 100644 --- a/spi25.c +++ b/spi25.c @@ -323,6 +323,16 @@ return 0; } +static int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay) +{ + /* FIXME: We can't tell if spi_read_status_register() failed. */ + /* FIXME: We don't time out. */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(poll_delay); + /* FIXME: Check the status register for errors. */ + return 0; +} + /** * Execute WREN plus another one byte `op`, optionally poll WIP afterwards. * @@ -348,13 +358,70 @@ if (result) msg_cerr("%s failed during command execution\n", __func__); - /* FIXME: We can't tell if spi_read_status_register() failed. */ - /* FIXME: We don't time out. */ - while (poll_delay && spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(poll_delay); - /* FIXME: Check the status register for errors. */ + const int status = poll_delay ? spi_poll_wip(flash, poll_delay) : 0; - return result; + return result ? result : status; +} + +static int spi_prepare_address(struct flashctx *const flash, + uint8_t cmd_buf[], const unsigned int addr) +{ + /* TODO: extend for 4BA */ + cmd_buf[1] = (addr >> 16) & 0xff; + cmd_buf[2] = (addr >> 8) & 0xff; + cmd_buf[3] = (addr >> 0) & 0xff; + return 3; +} + +/** + * Execute WREN plus another `op` that takes an address and + * optional data, poll WIP afterwards. + * + * @param flash the flash chip's context + * @param op the operation to execute + * @param addr the address parameter to `op` + * @param out_bytes bytes to send after the address, + * may be NULL iff `out_bytes` is 0 + * @param out_bytes number of bytes to send, 256 at most, may be zero + * @param poll_delay interval in us for polling WIP + * @return 0 on success, non-zero otherwise + */ +static int spi_write_cmd(struct flashctx *const flash, + const uint8_t op, const unsigned int addr, + const uint8_t *const out_bytes, const size_t out_len, + const unsigned int poll_delay) +{ + uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN + 256]; + struct spi_command cmds[] = { + { + .writecnt = 1, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + }, { + .writearr = cmd, + }, + NULL_SPI_CMD, + }; + + cmd[0] = op; + const int addr_len = spi_prepare_address(flash, cmd, addr); + if (addr_len < 0) + return 1; + + if (1 + addr_len + out_len > sizeof(cmd)) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(cmd + 1 + addr_len, out_bytes, out_len); + cmds[1].writecnt = 1 + addr_len + out_len; + + const int result = spi_send_multicommand(flash, cmds); + if (result) + msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); + + const int status = spi_poll_wip(flash, poll_delay); + + return result ? result : status; } int spi_chip_erase_60(struct flashctx *flash) @@ -378,43 +445,8 @@ int spi_block_erase_52(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_52_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_52, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 100-4000ms, so wait in 100ms steps. */ + return spi_write_cmd(flash, 0x52, addr, NULL, 0, 100 * 1000); } /* Block size is usually @@ -422,42 +454,8 @@ */ int spi_block_erase_c4(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_C4_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_C4, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 240-480 s, so wait in 500 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(500 * 1000 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 240-480s, so wait in 500ms steps. */ + return spi_write_cmd(flash, 0xc4, addr, NULL, 0, 500 * 1000); } /* Block size is usually @@ -468,43 +466,8 @@ int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_D8_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_D8, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 100-4000ms, so wait in 100ms steps. */ + return spi_write_cmd(flash, 0xd8, addr, NULL, 0, 100 * 1000); } /* Block size is usually @@ -513,207 +476,36 @@ int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_D7_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_D7, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 100-4000ms, so wait in 100ms steps. */ + return spi_write_cmd(flash, 0xd7, addr, NULL, 0, 100 * 1000); } /* Page erase (usually 256B blocks) */ int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_PE_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_PE, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - } }; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); - return result; - } - - /* Wait until the Write-In-Progress bit is cleared. - * This takes up to 20 ms usually (on worn out devices up to the 0.5s range), so wait in 1 ms steps. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This takes up to 20ms usually (on worn out devices + up to the 0.5s range), so wait in 1ms steps. */ + return spi_write_cmd(flash, 0xdb, addr, NULL, 0, 1 * 1000); } /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_SE_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_SE, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 15-800 ms, so wait in 10 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(10 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 15-800ms, so wait in 10ms steps. */ + return spi_write_cmd(flash, 0x20, addr, NULL, 0, 10 * 1000); } int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { -/* .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { */ - .writecnt = JEDEC_BE_50_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_50, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 10 ms, so wait in 1 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 10ms, so wait in 1ms steps. */ + return spi_write_cmd(flash, 0x50, addr, NULL, 0, 1 * 1000); } int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { -/* .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { */ - .writecnt = JEDEC_BE_81_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_81, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 8 ms, so wait in 1 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 8ms, so wait in 1ms steps. */ + return spi_write_cmd(flash, 0x81, addr, NULL, 0, 1 * 1000); } int spi_block_erase_60(struct flashctx *flash, unsigned int addr, @@ -784,101 +576,22 @@ } } -int spi_byte_program(struct flashctx *flash, unsigned int addr, - uint8_t databyte) +static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BYTE_PROGRAM, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff), - databyte - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - } - return result; -} - -int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) -{ - int result; - /* FIXME: Switch to malloc based on len unless that kills speed. */ - unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { - JEDEC_BYTE_PROGRAM, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr >> 0) & 0xff, - }; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, - .writearr = cmd, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - if (!len) { - msg_cerr("%s called for zero-length write\n", __func__); - return 1; - } - if (len > 256) { - msg_cerr("%s called for too long a write\n", __func__); - return 1; - } - - memcpy(&cmd[4], bytes, len); - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - } - return result; + return spi_write_cmd(flash, JEDEC_BYTE_PROGRAM, addr, bytes, len, 10); } int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes, unsigned int len) { - const unsigned char cmd[JEDEC_READ_OUTSIZE] = { - JEDEC_READ, - (address >> 16) & 0xff, - (address >> 8) & 0xff, - (address >> 0) & 0xff, - }; + uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN] = { JEDEC_READ, }; + + const int addr_len = spi_prepare_address(flash, cmd, address); + if (addr_len < 0) + return 1; /* Send Read */ - return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); + return spi_send_command(flash, 1 + addr_len, len, cmd, bytes); } /* @@ -989,7 +702,7 @@ for (i = start; i < start + len; i++) { result = (flash->chip->feature_bits & FEATURE_4BA_SUPPORT) == 0 - ? spi_byte_program(flash, i, buf[i - start]) + ? spi_nbyte_program(flash, i, buf + i - start, 1) : flash->chip->four_bytes_addr_funcs.program_byte(flash, i, buf[i - start]); if (result) return 1; @@ -1007,30 +720,6 @@ unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = { JEDEC_AAI_WORD_PROGRAM, }; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_AAI_WORD_PROGRAM, - (start >> 16) & 0xff, - (start >> 8) & 0xff, - (start & 0xff), - buf[0], - buf[1] - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; switch (flash->mst->spi.type) { #if CONFIG_INTERNAL == 1 @@ -1058,14 +747,6 @@ if (spi_chip_write_1(flash, buf, start, start % 2)) return SPI_GENERIC_ERROR; pos += start % 2; - cmds[1].writearr = (const unsigned char[]){ - JEDEC_AAI_WORD_PROGRAM, - (pos >> 16) & 0xff, - (pos >> 8) & 0xff, - (pos & 0xff), - buf[pos - start], - buf[pos - start + 1] - }; /* Do not return an error for now. */ //return SPI_GENERIC_ERROR; } @@ -1077,14 +758,9 @@ //return SPI_GENERIC_ERROR; } - - result = spi_send_multicommand(flash, cmds); - if (result != 0) { - msg_cerr("%s failed during start command execution: %d\n", __func__, result); + result = spi_write_cmd(flash, JEDEC_AAI_WORD_PROGRAM, start, buf + pos - start, 2, 10); + if (result) goto bailout; - } - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(10); /* We already wrote 2 bytes in the multicommand step. */ pos += 2; @@ -1098,8 +774,8 @@ msg_cerr("%s failed during followup AAI command execution: %d\n", __func__, result); goto bailout; } - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(10); + if (spi_poll_wip(flash, 10)) + goto bailout; } /* Use WRDI to exit AAI mode. This needs to be done before issuing any other non-AAI command. */ -- To view, visit https://review.coreboot.org/22383 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503 Gerrit-Change-Number: 22383 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[master]: spi25: Introduce spi_simple_write_cmd()
by Nico Huber (Code Review) 09 Nov '17

09 Nov '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22382 Change subject: spi25: Introduce spi_simple_write_cmd() ...................................................................... spi25: Introduce spi_simple_write_cmd() spi_simple_write_cmd() executes WREN plus a single byte write and polls WIP afterwards. It's used to replace current spi_erase_chip_*() imple- mentations. Change-Id: Ib244356fa471e15863b52e6037899d19113cb4a9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M flash.h M spi25.c 2 files changed, 39 insertions(+), 95 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/82/22382/1 diff --git a/flash.h b/flash.h index 62f2e34..b18d698 100644 --- a/flash.h +++ b/flash.h @@ -369,6 +369,7 @@ const unsigned char *writearr; unsigned char *readarr; }; +#define NULL_SPI_CMD { 0, 0, NULL, NULL, } int spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds); uint32_t spi_get_valid_read_addr(struct flashctx *flash); diff --git a/spi25.c b/spi25.c index 30b862f..da04d2e 100644 --- a/spi25.c +++ b/spi25.c @@ -22,6 +22,7 @@ * Contains the common SPI chip driver functions */ +#include <stddef.h> #include <string.h> #include "flash.h" #include "flashchips.h" @@ -322,114 +323,56 @@ return 0; } -int spi_chip_erase_60(struct flashctx *flash) +/** + * Execute WREN plus another one byte `op`, optionally poll WIP afterwards. + * + * @param flash the flash chip's context + * @param op the operation to execute + * @param poll_delay interval in us for polling WIP, don't poll if zero + * @return 0 on success, non-zero otherwise + */ +static int spi_simple_write_cmd(struct flashctx *const flash, const uint8_t op, const unsigned int poll_delay) { - int result; struct spi_command cmds[] = { { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, + .writecnt = 1, + .writearr = (const unsigned char[]){ JEDEC_WREN }, }, { - .writecnt = JEDEC_CE_60_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_CE_60 }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution\n", - __func__); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 1-85 s, so wait in 1 s steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1000 * 1000); + .writecnt = 1, + .writearr = (const unsigned char[]){ op }, + }, + NULL_SPI_CMD, + }; + + const int result = spi_send_multicommand(flash, cmds); + if (result) + msg_cerr("%s failed during command execution\n", __func__); + + /* FIXME: We can't tell if spi_read_status_register() failed. */ + /* FIXME: We don't time out. */ + while (poll_delay && spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(poll_delay); /* FIXME: Check the status register for errors. */ - return 0; + + return result; +} + +int spi_chip_erase_60(struct flashctx *flash) +{ + /* This usually takes 1-85s, so wait in 1s steps. */ + return spi_simple_write_cmd(flash, 0x60, 1000 * 1000); } int spi_chip_erase_62(struct flashctx *flash) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_CE_62_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_CE_62 }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution\n", - __func__); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 2-5 s, so wait in 100 ms steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 2-5s, so wait in 100ms steps. */ + return spi_simple_write_cmd(flash, 0x62, 100 * 1000); } int spi_chip_erase_c7(struct flashctx *flash) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_CE_C7_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_CE_C7 }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution\n", __func__); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 1-85 s, so wait in 1 s steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1000 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 1-85s, so wait in 1s steps. */ + return spi_simple_write_cmd(flash, 0xc7, 1000 * 1000); } int spi_block_erase_52(struct flashctx *flash, unsigned int addr, -- To view, visit https://review.coreboot.org/22382 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib244356fa471e15863b52e6037899d19113cb4a9 Gerrit-Change-Number: 22382 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: linux_spi: Dynamically detect max buffer size
by Nico Huber (Code Review) 08 Nov '17

08 Nov '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/22344 ) Change subject: linux_spi: Dynamically detect max buffer size ...................................................................... Patch Set 5: (5 comments) > I ended up re-writing a significant portion of this patch. Assuming > the changes look good, what's the "right" thing to do to get things > merged? Merge everything in this patch, or split my updates into a > follow-up patch? I think the changes should be done right away in this patch. In this case it wouldn't break anything in between two patches, but merging things that you know need an update feels generally wrong (bisect argument). The actual question we should ask is, who should do the changes? In this case, I would have asked Keno in advance if he wants to amend it (don't know if you did). Back to the patch: You can ignore all the new comments and nits, looks quite good actually :) But... I really care about the change to the spi_read_chunked() call. https://review.coreboot.org/#/c/22344/3/linux_spi.c File linux_spi.c: https://review.coreboot.org/#/c/22344/3/linux_spi.c@199 PS3, Line 199: The implementation currently does not support requests that > Re "why": As to not rely on the driver to split large transactions? I'm not No, I meant in the kernel. And the command is never written into the rx buffer anyway. Actually it seems that there is never a buffer that holds both tx and rx data throughout the whole stack starting with flashrom. https://review.coreboot.org/#/c/22344/5/linux_spi.c File linux_spi.c: https://review.coreboot.org/#/c/22344/5/linux_spi.c@136 PS5, Line 136: msg_pwarn("%s: Cannot open %s: %s.\n", __func__, BUF_SIZE_FROM_SYSFS, strerror(errno)); I was about to say, "function names in warnings?". But hey, we do it all over the place... https://review.coreboot.org/#/c/22344/5/linux_spi.c@143 PS5, Line 143: msg_pwarn("%s: Cannot read %s: %s.\n", __func__, BUF_SIZE_FROM_SYSFS, strerror(errno)); Nit, in the unlikely event that we are presented an empty file, we'd print: Cannot read /sys/module/spidev/parameters/bufsiz: Success. i.e. EOF is not an error :-/ https://review.coreboot.org/#/c/22344/5/linux_spi.c@154 PS5, Line 154: max_kernel_buf_size = (size_t)tmp; Nit, possible overflow. Very theoretic, don't know any environment where sizeof(size_t) < sizeof(long). https://review.coreboot.org/#/c/22344/5/linux_spi.c@163 PS5, Line 163: max_kernel_buf_size = (size_t)getpagesize(); getpagesize() is kind of deprecated, but we've used it before anyway. -- To view, visit https://review.coreboot.org/22344 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: Ic541e548ced8488f074d388f1c92174cad123064 Gerrit-Change-Number: 22344 Gerrit-PatchSet: 5 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: david.hendricks(a)gmail.com Gerrit-Comment-Date: Tue, 07 Nov 2017 14:19:32 +0000 Gerrit-HasComments: Yes

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Change in flashrom[refs/meta/config]: Allow only "flashrom developers" to submit (on all branches).
by build bot (Jenkins) (Code Review) 07 Nov '17

07 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22338 ) Change subject: Allow only "flashrom developers" to submit (on all branches). ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/flashrom-customrules/843/ : SUCCESS -- To view, visit https://review.coreboot.org/22338 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: refs/meta/config Gerrit-MessageType: comment Gerrit-Change-Id: I8dfc594c60292d03a36854f592c540e052c09c03 Gerrit-Change-Number: 22338 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Nov 2017 12:24:53 +0000 Gerrit-HasComments: No

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Change in flashrom[refs/meta/config]: Allow only "flashrom developers" to submit (on all branches).
by Patrick Georgi (Code Review) 07 Nov '17

07 Nov '17

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/22338 ) Change subject: Allow only "flashrom developers" to submit (on all branches). ...................................................................... Allow only "flashrom developers" to submit (on all branches). Change-Id: I8dfc594c60292d03a36854f592c540e052c09c03 Reviewed-on: https://review.coreboot.org/22338 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: Patrick Georgi <pgeorgi(a)google.com> --- M project.config 1 file changed, 2 insertions(+), 7 deletions(-) Approvals: Patrick Georgi: Verified; Looks good to me, approved diff --git a/project.config b/project.config index 157e80a..beb4ff3 100644 --- a/project.config +++ b/project.config @@ -4,12 +4,6 @@ requireChangeId = true [submit] action = cherry pick -[access "refs/heads/stable"] - exclusiveGroupPermissions = submit - submit = group flashrom developers -[access "refs/heads/staging"] - submit = group flashrom developers - exclusiveGroupPermissions = submit [access "refs/tags/*"] push = +force group flashrom developers exclusiveGroupPermissions = push @@ -39,10 +33,11 @@ owner = group user/Nico Huber (Nico) owner = group user/Stefan Tauner (stefanct) [access "refs/heads/*"] - exclusiveGroupPermissions = create delete + exclusiveGroupPermissions = create delete submit create = group user/David Hendricks (dhendrix) create = group user/Nico Huber (Nico) create = group user/Stefan Tauner (stefanct) delete = group user/David Hendricks (dhendrix) delete = group user/Nico Huber (Nico) delete = group user/Stefan Tauner (stefanct) + submit = group flashrom developers -- To view, visit https://review.coreboot.org/22338 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: refs/meta/config Gerrit-MessageType: merged Gerrit-Change-Id: I8dfc594c60292d03a36854f592c540e052c09c03 Gerrit-Change-Number: 22338 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[refs/meta/config]: Allow only "flashrom developers" to submit (on all branches).
by Patrick Georgi (Code Review) 07 Nov '17

07 Nov '17

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/22338 ) Change subject: Allow only "flashrom developers" to submit (on all branches). ...................................................................... Patch Set 3: Verified+1 Code-Review+2 -- To view, visit https://review.coreboot.org/22338 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: refs/meta/config Gerrit-MessageType: comment Gerrit-Change-Id: I8dfc594c60292d03a36854f592c540e052c09c03 Gerrit-Change-Number: 22338 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Nov 2017 12:24:38 +0000 Gerrit-HasComments: No

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Change in flashrom[refs/meta/config]: Allow only "flashrom developers" to submit (on all branches).
by build bot (Jenkins) (Code Review) 07 Nov '17

07 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22338 ) Change subject: Allow only "flashrom developers" to submit (on all branches). ...................................................................... Patch Set 3: Build Failed https://qa.coreboot.org/job/flashrom_gerrit/733/ : FAILURE https://qa.coreboot.org/job/flashrom-customrules/842/ : SUCCESS -- To view, visit https://review.coreboot.org/22338 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: refs/meta/config Gerrit-MessageType: comment Gerrit-Change-Id: I8dfc594c60292d03a36854f592c540e052c09c03 Gerrit-Change-Number: 22338 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Nov 2017 12:21:28 +0000 Gerrit-HasComments: No

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Change in flashrom[refs/meta/config]: Make Stefan, David and myself flashrom Owners
by build bot (Jenkins) (Code Review) 07 Nov '17

07 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22357 ) Change subject: Make Stefan, David and myself flashrom Owners ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/flashrom-customrules/841/ : SUCCESS -- To view, visit https://review.coreboot.org/22357 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: refs/meta/config Gerrit-MessageType: comment Gerrit-Change-Id: Ia8945aced4984dd84a7cc6db50adf1b486edf915 Gerrit-Change-Number: 22357 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Maximilian Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Nov 2017 12:16:43 +0000 Gerrit-HasComments: No

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