September 2024 - flashrom-gerrit

Change in flashrom[master]: pcidev: Fix typo
by Martijn Berger (Code Review) Aug. 29, 2026

Aug. 29, 2026

Martijn Berger has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39966 ) Change subject: pcidev: Fix typo ...................................................................... pcidev: Fix typo Fix typo Change-Id: If70834715a51dea4111ba56e85df0680ed25c7a4 Signed-off-by: Martijn Berger <martijn.berger(a)gmail.com> --- M pcidev.c M programmer.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/66/39966/1 diff --git a/pcidev.c b/pcidev.c index 973acde..38b9380 100644 --- a/pcidev.c +++ b/pcidev.c @@ -30,7 +30,7 @@ TYPE_UNKNOWN }; -int pci_bar_nuber_from_offset(int offset) +int pci_bar_number_from_offset(int offset) { switch (offset) { case PCI_BASE_ADDRESS_0: @@ -63,7 +63,7 @@ headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f; msg_pspew("PCI header type 0x%02x\n", headertype); - bar_number = pci_bar_nuber_from_offset(bar); + bar_number = pci_bar_number_from_offset(bar); if (PCI_LIB_VERSION >= 0x030500 && bar_number > -1) { addr = dev->base_addr[bar_number]; diff --git a/programmer.h b/programmer.h index 5d4c1d7..42f646b 100644 --- a/programmer.h +++ b/programmer.h @@ -190,7 +190,7 @@ // FIXME: This needs to be local, not global(?) extern struct pci_access *pacc; int pci_init_common(void); -int pci_bar_nuber_from_offset(int offset); +int pci_bar_number_from_offset(int offset); uintptr_t pcidev_readbar(struct pci_dev *dev, int bar); struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar); /* rpci_write_* are reversible writes. The original PCI config space register -- To view, visit https://review.coreboot.org/c/flashrom/+/39966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If70834715a51dea4111ba56e85df0680ed25c7a4 Gerrit-Change-Number: 39966 Gerrit-PatchSet: 1 Gerrit-Owner: Martijn Berger Gerrit-MessageType: newchange

5 9

Change in flashrom[master]: programmer: Introduce programmer alias mechanism
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38671 ) Change subject: programmer: Introduce programmer alias mechanism ...................................................................... programmer: Introduce programmer alias mechanism Originally introduced in the downstream commit ba0827acee4da6740133345f43aae386923bbaad . This was originally authored by David Hendricks so that the various flash peripheral in ChromeOS devices can be flashed. For example, flashrom -p ec -r ec.bin flashrom -p host -r host.bin Note that this requires, `CONFIG_DEFAULT_PROGRAMMER=PROGRAMMER_INTERNAL make` to be defined as build-time. BUG=b:148755493 BRANCH=none TEST=ran ./flashrom -p host --flash-name Change-Id: I73766451cd8900a9e0fe08efc7a4d81b2a35ac8d Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M cli_classic.c M it85spi.c M linux_mtd.c M linux_spi.c M programmer.c M programmer.h 6 files changed, 98 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/38671/1 diff --git a/cli_classic.c b/cli_classic.c index 73cc417..d58562b 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -329,13 +329,51 @@ break; } } - if (prog == PROGRAMMER_INVALID) { + + for (i = 0; aliases[i].name; i++) { + name = aliases[i].name; + namelen = strlen(aliases[i].name); + + if (strncmp(optarg, name, namelen)) + continue; + + switch (optarg[namelen]) { + case ':': + pparam = strdup(optarg + namelen + 1); + if (!strlen(pparam)) { + free(pparam); + pparam = NULL; + } + break; + case '\0': + break; + default: + /* The continue refers to the for-loop. + * It is here to be able to + * differentiate between foo and foobar. + */ + continue; + } + + alias = &aliases[i]; + msg_gdbg("Programmer alias: \"%s\", parameter: " + " \"%s\",\n", alias->name, pparam); + break; + } + + if ((prog == PROGRAMMER_INVALID) && !alias) { fprintf(stderr, "Error: Unknown programmer \"%s\". Valid choices are:\n", optarg); list_programmers_linebreak(0, 80, 0); msg_ginfo(".\n"); cli_classic_abort_usage(NULL); } + + if ((prog != PROGRAMMER_INVALID) && alias) { + fprintf(stderr, "Error: Alias cannot be used " + "with programmer name.\n"); + cli_classic_abort_usage(NULL); + } break; case 'R': /* print_version() is always called during startup. */ diff --git a/it85spi.c b/it85spi.c index 5ce9193..47e2337 100644 --- a/it85spi.c +++ b/it85spi.c @@ -289,6 +289,9 @@ { int ret; + if (!programming_ec()) + return 1; + if (!(internal_buses_supported & BUS_FWH)) { msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); return 1; diff --git a/linux_mtd.c b/linux_mtd.c index d2df95e..bee7cc5 100644 --- a/linux_mtd.c +++ b/linux_mtd.c @@ -363,6 +363,9 @@ int dev_num = 0; int ret = 1; + if (!programming_host()) + return 1; + param = extract_programmer_param("dev"); if (param) { char *endptr; diff --git a/linux_spi.c b/linux_spi.c index aa73c18..221a36e 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -78,6 +78,14 @@ const uint8_t mode = SPI_MODE_0; const uint8_t bits = 8; + /* + * FIXME: There might be other programmers with flash memory (such as + * an EC) connected via SPI. For now we rely on the device's driver to + * distinguish it and assume generic SPI implies host. + */ + if (!programming_host()) + return 1; + p = extract_programmer_param("spispeed"); if (p && strlen(p)) { speed_hz = (uint32_t)strtoul(p, &endp, 10) * 1000; diff --git a/programmer.c b/programmer.c index f4b4384..ffad784 100644 --- a/programmer.c +++ b/programmer.c @@ -128,6 +128,13 @@ return 0; } +struct programmer_alias aliases[] = { + { "ec", ALIAS_EC }, + { "host", ALIAS_HOST }, + { NULL }, +}; +struct programmer_alias *alias; + enum chipbustype get_buses_supported(void) { int i; diff --git a/programmer.h b/programmer.h index 3cf53b9..a7bd947 100644 --- a/programmer.h +++ b/programmer.h @@ -130,6 +130,44 @@ PROGRAMMER_INVALID /* This must always be the last entry. */ }; +enum alias_type { + ALIAS_NONE = 0, /* no alias (default) */ + ALIAS_EC, /* embedded controller */ + ALIAS_HOST, /* chipset / PCH / SoC / etc. */ +}; + +struct programmer_alias { + const char *name; + enum alias_type type; +}; + +extern struct programmer_alias *alias; +extern struct programmer_alias aliases[]; + +/** + * This function returns 'true' if current flashrom invocation is programming + * NONE. + */ +static inline int programming_none(void) { + return alias && (alias->type == ALIAS_NONE); +} + +/** + * This function returns 'true' if current flashrom invocation is programming + * the EC. + */ +static inline int programming_ec(void) { + return alias && (alias->type == ALIAS_EC); +} + +/** + * This function returns 'true' if current flashrom invocation is programming + * the HOST. + */ +static inline int programming_host(void) { + return alias && (alias->type == ALIAS_HOST); +} + enum programmer_type { PCI = 1, /* to detect uninitialized values */ USB, -- To view, visit https://review.coreboot.org/c/flashrom/+/38671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I73766451cd8900a9e0fe08efc7a4d81b2a35ac8d Gerrit-Change-Number: 38671 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Implement ich_hwseq_{read,write}_status() callbacks
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48135 ) Change subject: ichspi.c: Implement ich_hwseq_{read,write}_status() callbacks ...................................................................... ichspi.c: Implement ich_hwseq_{read,write}_status() callbacks This is needed to allow the opaque master in ichspi to R/W the SPI rom's status registers for write-protect support. BUG=b:174432470 TEST=builds Change-Id: I47e257838ebd0eda04e08d15fbd0fcc3e439c247 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/35/48135/1 diff --git a/ichspi.c b/ichspi.c index 45afe5b..7baea87 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1398,6 +1398,69 @@ return 1; } +static uint8_t ich_hwseq_read_status(const struct flashctx *flash) +{ + uint32_t hsfc; + uint32_t timeout = 5000 * 1000; + int len = 1; + uint8_t buf; + + msg_pdbg("Reading Status register\n"); + + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE32(ICH9_REG_HSFS, REGREAD32(ICH9_REG_HSFS)); + + hsfc = REGREAD32(ICH9_REG_HSFS); + hsfc &= ~HSFSC_FCYCLE; /* set read operation */ + + /* read status register */ + hsfc |= (0x8 << HSFSC_FCYCLE_OFF); + + hsfc &= ~HSFSC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((len - 1) << HSFSC_FDBC_OFF) & HSFSC_FDBC); + hsfc |= HSFSC_FGO; /* start */ + REGWRITE32(ICH9_REG_HSFS, hsfc); + if (ich_hwseq_wait_for_cycle_complete(timeout, len, g_ich_generation)) { + msg_perr("Reading Status register failed\n!!"); + return -1; + } + ich_read_data(&buf, len, ICH9_REG_FDATA0); + return buf; +} + +static int ich_hwseq_write_status(const struct flashctx *flash, int status) +{ + uint32_t hsfc; + uint32_t timeout = 5000 * 1000; + int len = 1; + uint8_t buf = status; + + msg_pdbg("Writing status register\n"); + + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE32(ICH9_REG_HSFS, REGREAD32(ICH9_REG_HSFS)); + + ich_fill_data(&buf, len, ICH9_REG_FDATA0); + hsfc = REGREAD32(ICH9_REG_HSFS); + hsfc &= ~HSFSC_FCYCLE; /* clear operation */ + + /* write status register */ + hsfc |= (0x7 << HSFSC_FCYCLE_OFF); + hsfc &= ~HSFSC_FDBC; /* clear byte count */ + + /* set byte count */ + hsfc |= (((len - 1) << HSFSC_FDBC_OFF) & HSFSC_FDBC); + hsfc |= HSFSC_FGO; /* start */ + REGWRITE32(ICH9_REG_HSFS, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len, g_ich_generation)) { + msg_perr("Writing Status register failed\n!!"); + return -1; + } + return 0; +} + static int ich_hwseq_probe(struct flashctx *flash) { uint32_t total_size, boundary; @@ -1798,6 +1861,8 @@ .read = ich_hwseq_read, .write = ich_hwseq_write, .erase = ich_hwseq_block_erase, + .read_status = ich_hwseq_read_status, + .write_status = ich_hwseq_write_status, }; int ich_init_spi(void *spibar, enum ich_chipset ich_gen) -- To view, visit https://review.coreboot.org/c/flashrom/+/48135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I47e257838ebd0eda04e08d15fbd0fcc3e439c247 Gerrit-Change-Number: 48135 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in flashrom[master]: ichspi.c: Implement ich_hwseq_get_flash_id()
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48133 ) Change subject: ichspi.c: Implement ich_hwseq_get_flash_id() ...................................................................... ichspi.c: Implement ich_hwseq_get_flash_id() Allow for decoding the SPI flash vid:did and to allow lookup and copying it from the flashchips database. This allows Flashrom to provide the user the real SPI flash chip name instead of 'Opaque flash chip'. before: ``` $ sudo ./flashrom -p internal --flash-name 2>&1 | grep 'Found ' Found chipset "Intel Kaby Lake U w/ iHDCP2.2 Prem.". Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. ``` after: ``` $ sudo ./flashrom -p internal --flash-name 2>&1 | grep 'Found ' Found chipset "Intel Kaby Lake U w/ iHDCP2.2 Prem.". Found Winbond flash chip "W25Q128.V" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. ``` BUG=none TEST=`flashrom -p internal --flash-name` Change-Id: Icdf684e21b19ee87b797092f3cf0353e1184291f Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 82 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/33/48133/1 diff --git a/ichspi.c b/ichspi.c index 4209d60..45afe5b 100644 --- a/ichspi.c +++ b/ichspi.c @@ -78,8 +78,17 @@ #define DLOCK_SSEQ_LOCKDN_OFF 16 #define DLOCK_SSEQ_LOCKDN (0x1 << DLOCK_SSEQ_LOCKDN_OFF) +/* Control bits */ +#define HSFSC_FGO_OFF 16 /* 0: Flash Cycle Go */ +#define HSFSC_FGO (0x1 << HSFSC_FGO_OFF) +#define HSFSC_FCYCLE_OFF 17 /* 17-20: FLASH Cycle */ +#define HSFSC_FCYCLE (0xf << HSFSC_FCYCLE_OFF) +#define HSFSC_FDBC_OFF 24 /* 24-29 : Flash Data Byte Count */ +#define HSFSC_FDBC (0x3f << HSFSC_FDBC_OFF) + #define PCH100_REG_FPR0 0x84 /* 32 Bits Protected Range 0 */ #define PCH100_REG_GPR0 0x98 /* 32 Bits Global Protected Range 0 */ +#define PCH100_REG_HSFSC 0x04 #define PCH100_REG_SSFSC 0xA0 /* 32 Bits Status (8) + Control (24) */ #define PCH100_REG_PREOP 0xA4 /* 16 Bits */ @@ -1321,12 +1330,85 @@ return 0; } +/* Given RDID info, return pointer to entry in flashchips[] */ +static const struct flashchip *flash_id_to_entry(uint32_t mfg_id, uint32_t model_id) +{ + const struct flashchip *chip; + + for (chip = &flashchips[0]; chip->vendor; chip++) { + if ((chip->manufacture_id == mfg_id) && + (chip->model_id == model_id)) + return chip; + } + + return NULL; +} + +static int ich_hwseq_get_flash_id(struct flashctx *flash, enum ich_chipset ich_gen) +{ + uint32_t hsfsc, data, mfg_id, model_id; + const struct flashchip *entry; + const int len = sizeof(data); + + /* make sure FDONE, FCERR, & AEL are cleared */ + REGWRITE32(ICH9_REG_HSFS, REGREAD32(ICH9_REG_HSFS)); + + /* Set RDID as flash cycle and FGO */ + hsfsc = REGREAD32(ICH9_REG_HSFS); + hsfsc &= ~HSFSC_FCYCLE; + hsfsc &= ~HSFSC_FDBC; + hsfsc |= ((len - 1) << HSFSC_FDBC_OFF) & HSFSC_FDBC; + hsfsc |= (0x6 << HSFSC_FCYCLE_OFF) | HSFSC_FGO; + REGWRITE32(ICH9_REG_HSFS, hsfsc); + /* poll for 100ms */ + if (ich_hwseq_wait_for_cycle_complete(100 * 1000, len, ich_gen)) { + msg_perr("Timed out waiting for RDID to complete.\n"); + return 0; + } + + /* + * Data will appear in reverse order: + * Byte 0: Manufacturer ID + * Byte 1: Model ID (MSB) + * Byte 2: Model ID (LSB) + */ + ich_read_data((uint8_t *)&data, len, ICH9_REG_FDATA0); + mfg_id = data & 0xff; + model_id = (data & 0xff00) | ((data >> 16) & 0xff); + + entry = flash_id_to_entry(mfg_id, model_id); + if (entry == NULL) { + msg_perr("Unable to identify chip, mfg_id: 0x%02x, " + "model_id: 0x%02x\n", mfg_id, model_id); + return 0; + } else { + msg_pdbg("Chip identified: %s\n", entry->name); + /* Update informational flash chip entries only */ + flash->chip->vendor = entry->vendor; + flash->chip->name = entry->name; + flash->chip->manufacture_id = entry->manufacture_id; + flash->chip->model_id = entry->model_id; + /* total_size read from flash descriptor */ + flash->chip->page_size = entry->page_size; + flash->chip->feature_bits = entry->feature_bits; + flash->chip->tested = entry->tested; + flash->chip->wp = entry->wp; + } + + return 1; +} + static int ich_hwseq_probe(struct flashctx *flash) { uint32_t total_size, boundary; uint32_t erase_size_low, size_low, erase_size_high, size_high; struct block_eraser *eraser; + if (ich_hwseq_get_flash_id(flash, ich_generation) != 1) { + msg_perr("Unable to read flash chip ID\n"); + return 0; + } + total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1; msg_cdbg("Hardware sequencing reports %d attached SPI flash chip", (hwseq_data.size_comp1 != 0) ? 2 : 1); -- To view, visit https://review.coreboot.org/c/flashrom/+/48133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icdf684e21b19ee87b797092f3cf0353e1184291f Gerrit-Change-Number: 48133 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: opaque: Implement opaque master hookable {read,write}_status callbacks
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48134 ) Change subject: opaque: Implement opaque master hookable {read,write}_status callbacks ...................................................................... opaque: Implement opaque master hookable {read,write}_status callbacks This allows for opaque masters to hook their own bespoke R/W primatives for status register manipulation. This is a pre-requirement to allow for ichspi to allow for write-protect support. BUG=b:174432470 TEST=builds Change-Id: I6fd8ba151dba2d0deb4b1dd86ba708d4fd3caeb9 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M chipdrivers.h M flashchips.c M opaque.c M programmer.h M spi25_statusreg.c 5 files changed, 36 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/48134/1 diff --git a/chipdrivers.h b/chipdrivers.h index cf03811..64a1d73 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -113,6 +113,8 @@ int read_opaque(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int write_opaque(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int erase_opaque(struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen); +uint8_t read_status_opaque(const struct flashctx *flash); +int write_status_opaque(const struct flashctx *flash, int status); /* at45db.c */ int probe_spi_at45db(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index c4ba4c6..e7b13a3 100644 --- a/flashchips.c +++ b/flashchips.c @@ -18930,6 +18930,8 @@ }, .write = write_opaque, .read = read_opaque, + .read_status = read_status_opaque, + .write_status = write_status_opaque, }, { diff --git a/opaque.c b/opaque.c index 276934f..de89181 100644 --- a/opaque.c +++ b/opaque.c @@ -46,6 +46,20 @@ return flash->mst->opaque.erase(flash, blockaddr, blocklen); } +uint8_t read_status_opaque(const struct flashctx *flash) +{ + if (flash->mst->opaque.read_status) + return flash->mst->opaque.read_status(flash); + return 1; +} + +int write_status_opaque(const struct flashctx *flash, int status) +{ + if (flash->mst->opaque.write_status) + return flash->mst->opaque.write_status(flash, status); + return 1; +} + int register_opaque_master(const struct opaque_master *mst) { struct registered_master rmst; diff --git a/programmer.h b/programmer.h index c93bf83..888c62c 100644 --- a/programmer.h +++ b/programmer.h @@ -722,6 +722,8 @@ int (*read) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int (*write) (struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int (*erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen); + uint8_t (*read_status) (const struct flashctx *flash); + int (*write_status) (const struct flashctx *flash, int status); const void *data; }; int register_opaque_master(const struct opaque_master *mst); diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 34f9ad4..a6d8676 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -83,11 +83,15 @@ "EWSR is needed\n"); feature_bits |= FEATURE_WRSR_EWSR; } - if (feature_bits & FEATURE_WRSR_WREN) - ret = spi_write_status_register_flag(flash, status, JEDEC_WREN); - if (ret && (feature_bits & FEATURE_WRSR_EWSR)) - ret = spi_write_status_register_flag(flash, status, JEDEC_EWSR); - return ret; + if (flash->chip->write_status) { + ret = flash->chip->write_status(flash, status); + } else { + if (feature_bits & FEATURE_WRSR_WREN) + ret = spi_write_status_register_flag(flash, status, JEDEC_WREN); + if (ret && (feature_bits & FEATURE_WRSR_EWSR)) + ret = spi_write_status_register_flag(flash, status, JEDEC_EWSR); + } + return ret; } uint8_t spi_read_status_register(const struct flashctx *flash) @@ -95,16 +99,17 @@ static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; /* FIXME: No workarounds for driver/hardware bugs in generic code. */ unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */ - int ret; + int ret = 0; /* Read Status Register */ - ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); - if (ret) { + if (flash->chip->read_status) + readarr[0] = flash->chip->read_status(flash); + else + ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + if (ret) msg_cerr("RDSR failed!\n"); - /* FIXME: We should propagate the error. */ - return 0; - } + /* FIXME: We should propagate the error. */ return readarr[0]; } -- To view, visit https://review.coreboot.org/c/flashrom/+/48134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6fd8ba151dba2d0deb4b1dd86ba708d4fd3caeb9 Gerrit-Change-Number: 48134 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 1

Change in flashrom[master]: udelay.c: Enable providing delay calibration value through CLI
by Hrvoje Čavrak (Code Review) Aug. 29, 2026

Aug. 29, 2026

Hrvoje Čavrak has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44517 ) Change subject: udelay.c: Enable providing delay calibration value through CLI ...................................................................... udelay.c: Enable providing delay calibration value through CLI This commit implements --get-loop-delay/--set-loop-delay options to retrieve and provide the calibration loop delay through the command line. The delay calibration procedure can take up to few seconds, which adds up when executed a number of times consecutively. Therefore, this provides a means to execute it only once, and then re-use the calibrated value on subsequent runs. Also, it implements a sanity check, expecting the value to land within 10% of the theoretical delay expectance, otherwise it ignores the provided value and runs the calibration procedure instead. Signed-off-by: Hrvoje Cavrak <hrvoje(a)hrvoje.org> Change-Id: I7c9a491c5cb5fb3af56a691a0c6af9b53dcff550 --- M cli_classic.c M flashrom.8.tmpl M libflashrom.c M programmer.h M udelay.c 5 files changed, 60 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/44517/1 diff --git a/cli_classic.c b/cli_classic.c index 967ff50..b023c45 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -63,6 +63,8 @@ " -o | --output <logfile> log output to <logfile>\n" " --flash-contents <ref-file> assume flash contents to be <ref-file>\n" " -L | --list-supported print supported devices\n" + " --set-loop-delay <value> set loop delay calibration manually\n" + " --get-loop-delay retrieve loop delay calibration\n" #if CONFIG_PRINT_WIKI == 1 " -z | --list-supported-wiki print supported devices in wiki syntax\n" #endif @@ -118,6 +120,7 @@ int flash_name = 0, flash_size = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; int dont_verify_it = 0, dont_verify_all = 0, list_supported = 0, operation_specified = 0; + unsigned long provided_delay = 0; struct flashrom_layout *layout = NULL; enum programmer prog = PROGRAMMER_INVALID; enum { @@ -127,6 +130,8 @@ OPTION_FLASH_CONTENTS, OPTION_FLASH_NAME, OPTION_FLASH_SIZE, + OPTION_GET_LOOP_DELAY, + OPTION_SET_LOOP_DELAY, }; int ret = 0; @@ -156,6 +161,8 @@ {"help", 0, NULL, 'h'}, {"version", 0, NULL, 'R'}, {"output", 1, NULL, 'o'}, + {"get-loop-delay", 0, NULL, OPTION_GET_LOOP_DELAY}, + {"set-loop-delay", 1, NULL, OPTION_SET_LOOP_DELAY}, {NULL, 0, NULL, 0}, }; @@ -365,6 +372,14 @@ } #endif /* STANDALONE */ break; + case OPTION_GET_LOOP_DELAY: + /* Make it easy for scripts to parse this by omitting anything else */ + msg_pinfo("%lu\n", get_calibration_value()); + exit(0); + break; + case OPTION_SET_LOOP_DELAY: + provided_delay = strtoul(strdup(optarg), NULL, 0); + break; default: cli_classic_abort_usage(NULL); break; @@ -457,7 +472,10 @@ } /* FIXME: Delay calibration should happen in programmer code. */ - myusec_calibrate_delay(); + if (provided_delay) + set_external_calibration(provided_delay); + else + myusec_calibrate_delay(0); if (programmer_init(prog, pparam)) { msg_perr("Error: Programmer initialization failed.\n"); diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index db50d59..4aada91 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -50,7 +50,7 @@ [\fB\-E\fR|\fB\-r\fR <file>|\fB\-w\fR <file>|\fB\-v\fR <file>] [(\fB\-l\fR <file>|\fB\-\-ifd|\fB \-\-fmap\fR|\fB\-\-fmap-file\fR <file>) [\fB\-i\fR <image>]] [\fB\-n\fR] [\fB\-N\fR] [\fB\-f\fR])] - [\fB\-V\fR[\fBV\fR[\fBV\fR]]] [\fB-o\fR <logfile>] + [\fB\-V\fR[\fBV\fR[\fBV\fR]]] [\fB-o\fR <logfile>] [\fB-d\fR get | <value>] .SH DESCRIPTION .B flashrom is a utility for detecting, reading, writing, verifying and erasing flash @@ -364,6 +364,17 @@ .TP .B "\-R, \-\-version" Show version information and exit. +.TP +.B "\-\-get\-loop\-delay" +Retrieve the loop calibration delay value or provide one externally. Calibrate +delay procedure can take a few seconds and for repeated execution on a large +number of hosts it can provide a significant overhead. By getting the value, +it can later be provided by \-\-set\-loop\-delay +.TP +.B "\-\-set\-loop\-delay <value>" +This argument makes it possible to provide the calibration delay through the +command line option. + .SH PROGRAMMER-SPECIFIC INFORMATION Some programmer drivers accept further parameters to set programmer-specific parameters. These parameters are separated from the programmer name by a diff --git a/libflashrom.c b/libflashrom.c index ae2d33d..92e2527 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -51,7 +51,7 @@ { if (perform_selfcheck && selfcheck()) return 1; - myusec_calibrate_delay(); + myusec_calibrate_delay(0); return 0; } diff --git a/programmer.h b/programmer.h index c5cab18..e0925e2 100644 --- a/programmer.h +++ b/programmer.h @@ -280,9 +280,11 @@ /* udelay.c */ void myusec_delay(unsigned int usecs); -void myusec_calibrate_delay(void); +void myusec_calibrate_delay(int force); void internal_sleep(unsigned int usecs); void internal_delay(unsigned int usecs); +unsigned long get_calibration_value(void); +void set_external_calibration(unsigned long external_micro); #if CONFIG_INTERNAL == 1 /* board_enable.c */ diff --git a/udelay.c b/udelay.c index 6c0efc4..698f1ca 100644 --- a/udelay.c +++ b/udelay.c @@ -133,9 +133,9 @@ return timeusec; } -void myusec_calibrate_delay(void) +void myusec_calibrate_delay(int force) { - if (clock_check_res()) + if (clock_check_res() && !force) return; unsigned long count = 1000; @@ -221,6 +221,28 @@ msg_pinfo("OK.\n"); } +void set_external_calibration(unsigned long external_micro) +{ + micro = external_micro; + unsigned long elapsed = measure_delay(100000); + /* Do a sanity check if the provided parameter makes loops fall + * within 10% of the desired value. Otherwise, ignore provided value + * and recalibrate. + */ + if (elapsed > 90000 && elapsed < 110000) + msg_pinfo("Provided delay is acceptable!\n"); + else { + msg_pinfo("Elapsed: %lu, provided delay is NOT acceptable!\n", elapsed); + myusec_calibrate_delay(1); /* Ignore using the system clock for loop timing */ + } +} + +unsigned long get_calibration_value(void) +{ + myusec_calibrate_delay(1); /* Ignore using the system clock for loop timing */ + return micro; +} + /* Not very precise sleep. */ void internal_sleep(unsigned int usecs) { @@ -250,7 +272,7 @@ #else #include <libpayload.h> -void myusec_calibrate_delay(void) +void myusec_calibrate_delay(int force) { get_cpu_speed(); } -- To view, visit https://review.coreboot.org/c/flashrom/+/44517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7c9a491c5cb5fb3af56a691a0c6af9b53dcff550 Gerrit-Change-Number: 44517 Gerrit-PatchSet: 1 Gerrit-Owner: Hrvoje Čavrak <github(a)hrvoje.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi: print transaction error in debug mode
by Jonathan Zhang (Code Review) Aug. 29, 2026

Aug. 29, 2026

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49001 ) Change subject: ichspi: print transaction error in debug mode ...................................................................... ichspi: print transaction error in debug mode When "--fmap" option is used, flashrom does binary search in flash for fmap. When it reads flash region that is locked, transaction error happens. Print transaction error in debug mode, so that following message: Transaction error between offset 0x02cb4000 and 0x02cb4007 (= 0x02cb4000 + 7)! shows up only when "-V" is specified. Change-Id: Iebed1ae7f15b7f06b90a0b5947b953f7f0e1567d Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> --- M ichspi.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/01/49001/1 diff --git a/ichspi.c b/ichspi.c index 4209d60..6dde7b2 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1311,11 +1311,17 @@ if (hsfs & HSFS_FCERR) { addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask; - msg_perr("Transaction error between offset 0x%08x and " + + /* + * If the partition is locked, this transaction error happens. + * Print in verbose mode to avoid excessive messages. + */ + msg_cdbg("Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); prettyprint_ich9_reg_hsfs(hsfs, ich_gen); prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC), ich_gen); + return 1; } return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/49001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iebed1ae7f15b7f06b90a0b5947b953f7f0e1567d Gerrit-Change-Number: 49001 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: cbtable.c: don't assume high addresses can fully map 1MB
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/45521 ) Change subject: cbtable.c: don't assume high addresses can fully map 1MB ...................................................................... cbtable.c: don't assume high addresses can fully map 1MB I do not know a clean way to compose find_lb_table() and find_lb_table_remap() or why this cannot always been done. However this is a fix ported from downstream found here: https://chromium-review.googlesource.com/685608 Change-Id: Ibf2323a0a793f693928b81c64acd09bb932a6b98 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M cbtable.c 1 file changed, 61 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/45521/1 diff --git a/cbtable.c b/cbtable.c index 6185f12..6dd4059 100644 --- a/cbtable.c +++ b/cbtable.c @@ -205,8 +205,68 @@ msg_pdbg("Found coreboot table at 0x%08lx.\n", addr); return head; + }; + + return NULL; +} + +static struct lb_header *find_lb_table_remap(unsigned long start_addr, + uint8_t **table_area) +{ + size_t offset; + unsigned long addr, end; + size_t mapping_size; + void *base; + + mapping_size = getpagesize(); + offset = start_addr % getpagesize(); + start_addr -= offset; + + base = physmap_ro("high tables", start_addr, mapping_size); + if (ERROR_PTR == base) { + msg_perr("Failed getting access to coreboot high tables.\n"); + return NULL; } + for (addr = offset, end = getpagesize(); addr < end; addr += 16) { + struct lb_record *recs; + struct lb_header *head; + + /* No more headers to check. */ + if (end - addr < sizeof(*head)) + return NULL; + + head = (struct lb_header *)(((char *)base) + addr); + + if (!lb_header_valid(head, addr)) + continue; + + if (mapping_size - addr < head->table_bytes + sizeof(*head)) { + size_t prev_mapping_size = mapping_size; + mapping_size = head->table_bytes + sizeof(*head); + mapping_size += addr; + mapping_size += getpagesize() - + (mapping_size % getpagesize()); + physunmap(base, prev_mapping_size); + base = physmap_ro("high tables", start_addr, + mapping_size); + if (ERROR_PTR == base) { + msg_perr("Failed getting access to coreboot high tables.\n"); + return NULL; + } + } + + head = (struct lb_header *)(((char *)base) + addr); + recs = + (struct lb_record *)(((char *)base) + addr + sizeof(*head)); + if (!lb_table_valid(head, recs)) + continue; + msg_pdbg("Found coreboot table at 0x%08lx.\n", addr); + *table_area = base; + return head; + } + + physunmap(base, mapping_size); return NULL; } @@ -283,15 +343,9 @@ (((char *)lb_table) + lb_table->header_bytes); if (forward->tag == LB_TAG_FORWARD) { start = forward->forward; - start &= ~(getpagesize() - 1); physunmap_unaligned(table_area, BYTES_TO_MAP); // FIXME: table_area is never unmapped below, nor is it unmapped above in the no-forward case - table_area = physmap_ro_unaligned("high tables", start, BYTES_TO_MAP); - if (ERROR_PTR == table_area) { - msg_perr("Failed getting access to coreboot high tables.\n"); - return -1; - } - lb_table = find_lb_table(table_area, 0x00000, 0x1000); + lb_table = find_lb_table_remap(start, &table_area); } } -- To view, visit https://review.coreboot.org/c/flashrom/+/45521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ibf2323a0a793f693928b81c64acd09bb932a6b98 Gerrit-Change-Number: 45521 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: [WIP]spi25.c: Implement fast read
by Arthur Heymans (Code Review) Aug. 29, 2026

Aug. 29, 2026

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33034 Change subject: [WIP]spi25.c: Implement fast read ...................................................................... [WIP]spi25.c: Implement fast read Use the fast read OP by default and fall back to regular read if that failed. Change-Id: I96393e1beea0164daa8e366a1d09a573f2c6d16f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M ichspi.c M spi.h M spi25.c 3 files changed, 23 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/33034/1 diff --git a/ichspi.c b/ichspi.c index 0f1470d..54cb1f9 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1117,14 +1117,14 @@ opcode = &(curopcodes->opcode[opcode_index]); /* The following valid writecnt/readcnt combinations exist: - * writecnt = 4, readcnt >= 0 + * writecnt = 4 or 5, readcnt >= 0 (The dummy bit on fast reads gets discarded) * writecnt = 1, readcnt >= 0 * writecnt >= 4, readcnt = 0 * writecnt >= 1, readcnt = 0 * writecnt >= 1 is guaranteed for all commands. */ if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) && - (writecnt != 4)) { + ((writecnt != 4) && (writecnt != 5))) { msg_perr("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want =4\n", __func__, cmd, writecnt); diff --git a/spi.h b/spi.h index 0073c71..65dc033 100644 --- a/spi.h +++ b/spi.h @@ -149,6 +149,7 @@ /* Read the memory */ #define JEDEC_READ 0x03 #define JEDEC_READ_OUTSIZE 0x04 +#define JEDEC_FAST_READ 0x0b /* JEDEC_READ_INSIZE : any length */ /* Read the memory (with delay after sending address) */ @@ -168,6 +169,7 @@ /* Read the memory with 4-byte address From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ #define JEDEC_READ_4BA 0x13 +#define JEDEC_FAST_READ_4BA 0x0c /* Read the memory with 4-byte address (and delay after sending address) From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ diff --git a/spi25.c b/spi25.c index 8b6c462..36d2436 100644 --- a/spi25.c +++ b/spi25.c @@ -645,12 +645,30 @@ unsigned int len) { const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_READ && spi_master_4ba(flash); - uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN] = { native_4ba ? JEDEC_READ_4BA : JEDEC_READ, }; + bool fast_read = true; + uint8_t cmd[2 + JEDEC_MAX_ADDR_LEN]; + + if (native_4ba) + fast_read = flash->chip->feature_bits & FEATURE_4BA_FAST_READ; + + if (fast_read) + cmd[0] = native_4ba ? JEDEC_FAST_READ_4BA : JEDEC_FAST_READ; + else + cmd[0] = native_4ba ? JEDEC_READ_4BA : JEDEC_READ; const int addr_len = spi_prepare_address(flash, cmd, native_4ba, address); if (addr_len < 0) return 1; + if (fast_read) { + cmd[addr_len + 1] = 0; + int ret = spi_send_command(flash, 2 + addr_len, len, cmd, bytes); + if (!ret) + return ret; + msg_cinfo("%s: Fast Read did not succeed, falling back to regular read", __func__); + cmd[0] = native_4ba ? JEDEC_READ_4BA : JEDEC_READ; + } + /* Send Read */ return spi_send_command(flash, 1 + addr_len, len, cmd, bytes); } -- To view, visit https://review.coreboot.org/c/flashrom/+/33034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I96393e1beea0164daa8e366a1d09a573f2c6d16f Gerrit-Change-Number: 33034 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in flashrom[master]: nicintel: add I350 support
by Martijn Berger (Code Review) Aug. 29, 2026

Aug. 29, 2026

Martijn Berger has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39963 ) Change subject: nicintel: add I350 support ...................................................................... nicintel: add I350 support While trying to flash I350 Intel NIC's on arm64 linux I had to change some things to make it work well Change-Id: Id203d2ce247cf39a8d650887322ccced0151c6a9 Signed-off-by: Martijn Berger <martijn.berger(a)gmail.com> --- M nicintel_eeprom.c M nicintel_spi.c 2 files changed, 39 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/63/39963/1 diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index 4d45f79..be03e41 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -27,6 +27,9 @@ * 8.4.3: EEPROM-Mode Read Register * 8.4.6: EEPROM-Mode Write Register * Write process inspired on kernel e1000_i210.c + * + * Intel I350 Gigabit controller Datasheet + * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/eth… */ #include <stdlib.h> @@ -75,8 +78,6 @@ static struct pci_dev *nicintel_pci; static bool done_i20_write = false; -#define UNPROG_DEVICE 0x1509 - /* * Warning: is_i210() below makes assumptions on these PCI ids. * It may have to be updated when this list is extended. @@ -87,7 +88,7 @@ {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"}, {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, - {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, + {PCI_VENDOR_ID_INTEL, 0x1509, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x1531, NT, "Intel", "I210 Gigabit Network Connection Unprogrammed"}, {PCI_VENDOR_ID_INTEL, 0x1532, NT, "Intel", "I211 Gigabit Network Connection Unprogrammed"}, {PCI_VENDOR_ID_INTEL, 0x1533, OK, "Intel", "I210 Gigabit Network Connection"}, @@ -95,9 +96,26 @@ {PCI_VENDOR_ID_INTEL, 0x1537, NT, "Intel", "I210 Gigabit Network Connection SERDES Backplane"}, {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"}, {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x151f, OK, "Intel", "I350 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1521, OK, "Intel", "I350 Gigabit Network Connection Copper"}, + {PCI_VENDOR_ID_INTEL, 0x1522, NT, "Intel", "I350 Gigabit Network Connection Fiber"}, + {PCI_VENDOR_ID_INTEL, 0x1523, NT, "Intel", "I350 Gigabit Network Connection 1000BASE-KX / 1000BASE-BX backplane"}, + {PCI_VENDOR_ID_INTEL, 0x1522, NT, "Intel", "I350 Gigabit Network Connection External SGMII PHY"}, {0}, }; +static inline bool is_unprog_device(uint16_t device_id) +{ + switch (device_id) + { + case 0x1509: // Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller + case 0x151f: // I350 Gigabit Network Connection Unprogrammed + return true; + default: + return false; + } +} + static inline bool is_i210(uint16_t device_id) { return (device_id & 0xfff0) == 0x1530; @@ -118,7 +136,7 @@ static int nicintel_ee_probe_82580(struct flashctx *flash) { - if (nicintel_pci->device_id == UNPROG_DEVICE) + if (is_unprog_device(nicintel_pci->device_id)) flash->chip->total_size = 16; /* Fall back to minimum supported size. */ else { uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); @@ -456,7 +474,7 @@ if (!dev) return 1; - uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + uintptr_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); if (!io_base_addr) return 1; @@ -466,7 +484,7 @@ return 1; nicintel_pci = dev; - if ((dev->device_id != UNPROG_DEVICE)) { + if (!is_unprog_device(dev->device_id)) { uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting diff --git a/nicintel_spi.c b/nicintel_spi.c index 1173ef7..09a37dc 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -28,6 +28,9 @@ * * Intel 82599 10 GbE Controller Datasheet (331520) * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/8259… + * + * Intel I350 Gigabit controller Datasheet + * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/eth… */ #include <stdlib.h> @@ -104,6 +107,11 @@ {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"}, {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x151f, NT, "Intel", "I350 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1521, NT, "Intel", "I350 Gigabit Network Connection Copper"}, + {PCI_VENDOR_ID_INTEL, 0x1522, NT, "Intel", "I350 Gigabit Network Connection Fiber"}, + {PCI_VENDOR_ID_INTEL, 0x1523, NT, "Intel", "I350 Gigabit Network Connection 1000BASE-KX / 1000BASE-BX backplane"}, + {PCI_VENDOR_ID_INTEL, 0x1522, NT, "Intel", "I350 Gigabit Network Connection External SGMII PHY"}, {0}, }; @@ -252,7 +260,7 @@ if (!dev) return 1; - uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + uintptr_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); if (!io_base_addr) return 1; @@ -266,6 +274,12 @@ MEMMAP_SIZE); if (!nicintel_spibar || nicintel_spi_82599_enable_flash()) return 1; + } else if ((dev->device_id & 0xfff0) == 0x1510 || + (dev->device_id & 0xfff0) == 0x1520) { + nicintel_spibar = rphysmap("Intel I350 Gigabit w/ SPI flash", io_base_addr, + MEMMAP_SIZE); + if (!nicintel_spibar || nicintel_spi_i210_enable_flash()) + return 1; } else { nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, MEMMAP_SIZE); -- To view, visit https://review.coreboot.org/c/flashrom/+/39963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id203d2ce247cf39a8d650887322ccced0151c6a9 Gerrit-Change-Number: 39963 Gerrit-PatchSet: 1 Gerrit-Owner: Martijn Berger Gerrit-MessageType: newchange

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