August 2024 - flashrom-gerrit - mail.coreboot.org

[S] Change in flashrom[main]: flashchips: add GD25B256E and GD25R256E
by Anastasia Klimchuk (Code Review) 27 Aug '24

27 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83998?usp=email ) Change subject: flashchips: add GD25B256E and GD25R256E ...................................................................... flashchips: add GD25B256E and GD25R256E removed FEATURE_WRSR_EXT2 from the model after datasheet review. replace printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, .unlock = SPI_DISABLE_BLOCKPROTECT, with .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, GD25B256E: 3V 256Mbit, Quad enabled. GD25R256E: GD25B256E features + RPMC, so they share the same datasheet on flash side https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-0… Tested both models on ch347 with erase, write, read and protection. Change-Id: Ie733e0c2e35fa4797f5198f2c8334469b65f402c Signed-off-by: Victor Lim <vlim(a)gigadevice.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83998 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c M include/flashchips.h 2 files changed, 6 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 40a3f2b..0c8517f 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7583,14 +7583,13 @@ { .vendor = "GigaDevice", - .name = "GD25Q256D/GD25Q256E", + .name = "GD25Q256E/GD25B256E/GD25R256E/GD25Q256D", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q256D, .total_size = 32768, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | - FEATURE_WRSR_EXT2 | FEATURE_WRSR2 | FEATURE_WRSR3, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2 | FEATURE_WRSR3, .tested = TEST_OK_PREWB, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, @@ -7622,8 +7621,8 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, - .unlock = SPI_DISABLE_BLOCKPROTECT, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, .voltage = {2700, 3600}, @@ -7632,7 +7631,7 @@ .srp = {STATUS1, 7, RW}, .srl = {STATUS2, 6, RW}, .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, - .tb = {STATUS1, 6, RW}, + .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */ }, .decode_range = DECODE_RANGE_SPI25, }, diff --git a/include/flashchips.h b/include/flashchips.h index 02de72a..4456587 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -395,7 +395,7 @@ #define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */ #define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */ #define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C,and GD25Q128E, GD25B128E, GD25R128E can be distinguished by SFDP */ -#define GIGADEVICE_GD25Q256D 0x4019 +#define GIGADEVICE_GD25Q256D 0x4019 /* Same as GD25B256E, GD25Q256E, GD25R256E */ #define GIGADEVICE_GD25VQ21B 0x4212 #define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */ #define GIGADEVICE_GD25VQ80C 0x4214 -- To view, visit https://review.coreboot.org/c/flashrom/+/83998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie733e0c2e35fa4797f5198f2c8334469b65f402c Gerrit-Change-Number: 83998 Gerrit-PatchSet: 5 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: ch347_spi: Add spi clock frequency selection
by Nicholas Chin (Code Review) 26 Aug '24

26 Aug '24

Attention is currently required from: ZhiYuanNJ. Nicholas Chin has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email ) Change subject: ch347_spi: Add spi clock frequency selection ...................................................................... Patch Set 14: Code-Review+2 (1 comment) Patchset: PS14: > Nicholas, just wanted to check, do you approve the idea that we go ahead with the patch to add the f […] That's fine with me. -- To view, visit https://review.coreboot.org/c/flashrom/+/82776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Gerrit-Change-Number: 82776 Gerrit-PatchSet: 14 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ZhiYuanNJ Gerrit-Comment-Date: Mon, 26 Aug 2024 12:47:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: flashchips: add GD25B256E and GD25R256E
by Anastasia Klimchuk (Code Review) 26 Aug '24

26 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/83998?usp=email ) Change subject: flashchips: add GD25B256E and GD25R256E ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Patchset: PS4: Victor, good news, I rebased the patch again and now it got verified successfully! So it's all good, I will submit it tomorrow. Sorry for inconvenience. The difference could be that I rebased on top of main branch. In comparison, for you locally this patch was a part of the chain, and so it was by default rebased on top of parent commit. And that parent commit was already submitted, so there was no actual difference of rebasing on the same parent again. -- To view, visit https://review.coreboot.org/c/flashrom/+/83998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie733e0c2e35fa4797f5198f2c8334469b65f402c Gerrit-Change-Number: 83998 Gerrit-PatchSet: 4 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 26 Aug 2024 09:20:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in flashrom[main]: ch347_spi: Add spi clock frequency selection
by Anastasia Klimchuk (Code Review) 26 Aug '24

26 Aug '24

Attention is currently required from: Nicholas Chin, ZhiYuanNJ. Anastasia Klimchuk has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email ) Change subject: ch347_spi: Add spi clock frequency selection ...................................................................... Patch Set 14: Code-Review+2 (3 comments) Patchset: PS14: Nicholas, just wanted to check, do you approve the idea that we go ahead with the patch to add the feature with the same default as before (15MHz)? And then later, if decided so, the default can be changed in a separate patch. File ch347_spi.c: https://review.coreboot.org/c/flashrom/+/82776/comment/c594fba9_4068856e?us… : PS11, Line 291: speed_index = 1; > But you haven't done? :) […] Done File ch347_spi.c: https://review.coreboot.org/c/flashrom/+/82776/comment/491a81e1_d6d8fb84?us… : PS13, Line 291: int speed_index = 2; > Good sense， sorry for the slow response, updated. All good , thank you! -- To view, visit https://review.coreboot.org/c/flashrom/+/82776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Gerrit-Change-Number: 82776 Gerrit-PatchSet: 14 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ZhiYuanNJ Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 26 Aug 2024 09:12:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: ZhiYuanNJ

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[XS] Change in flashrom[main]: flashchips: Update test status for Fudan FM25Q08 and FM25Q128
by Anastasia Klimchuk (Code Review) 26 Aug '24

26 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83970?usp=email ) Change subject: flashchips: Update test status for Fudan FM25Q08 and FM25Q128 ...................................................................... flashchips: Update test status for Fudan FM25Q08 and FM25Q128 Both of these chips were tested in-circuit with an SOIC-8 clamp and two different BusPirate boards: the BPv3.6 from Adafruit (sku 237) and the BPv3.6a from Sparkfun (sku TOL-12942), on a Fedora 38 host, using flashrom 9a570318 (changes rebased since then). Change-Id: Ib3c94f03a132a912bb4bb9d36e8783f4468587c4 Signed-off-by: Samantaz Fox <coding(a)samantaz.fr> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83970 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M flashchips.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Anastasia Klimchuk: Looks good to me, approved build bot (Jenkins): Verified diff --git a/flashchips.c b/flashchips.c index e842ebe..40a3f2b 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6240,7 +6240,7 @@ /* OTP: 1024B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ /* QPI enable 0x38, disable 0xFF */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -6403,7 +6403,7 @@ /* supports SFDP */ /* QPI enable 0x38, disable 0xFF */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = { -- To view, visit https://review.coreboot.org/c/flashrom/+/83970?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ib3c94f03a132a912bb4bb9d36e8783f4468587c4 Gerrit-Change-Number: 83970 Gerrit-PatchSet: 3 Gerrit-Owner: Samantaz Fox <coding(a)samantaz.fr> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: flashchips: Add definitions for Fudan FM25Q04, FM25Q64 and FM25Q128
by Anastasia Klimchuk (Code Review) 26 Aug '24

26 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83969?usp=email ) Change subject: flashchips: Add definitions for Fudan FM25Q04, FM25Q64 and FM25Q128 ...................................................................... flashchips: Add definitions for Fudan FM25Q04, FM25Q64 and FM25Q128 These chips have the exact same characteristics as their 8/16/32 counterparts, except for the different flash size. Relevant datasheets (I've also included the FM25Q32 as a reference): * https://www.fmsh.com/nvm/FM25Q04_ds_eng.pdf * https://www.fmsh.com/nvm/FM25Q32_ds_eng.pdf * https://www.fmsh.com/nvm/FM25Q64_ds_eng.pdf * https://www.fmsh.com/nvm/FM25Q128_ds_eng.pdf Testing status will be updated in a subsequent commit. Change-Id: I88fcc2bbb9706c8adb3722da6aa0e1d2d04c3fde Signed-off-by: Samantaz Fox <coding(a)samantaz.fr> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83969 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c M include/flashchips.h 2 files changed, 135 insertions(+), 0 deletions(-) Approvals: Anastasia Klimchuk: Looks good to me, approved build bot (Jenkins): Verified diff --git a/flashchips.c b/flashchips.c index a498ded..e842ebe 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6186,6 +6186,50 @@ { .vendor = "Fudan", + .name = "FM25Q04", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25Q04, + .total_size = 512, + .page_size = 256, + /* supports SFDP */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + /* 128 * 4KB sectors */ + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + /* 16 * 32KB blocks */ + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + /* 8 * 64KB blocks */ + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + /* Full chip erase (0x60) */ + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + /* Full chip erase (0xC7) */ + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + }, + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP2_TB_BPL, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP2_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Fudan", .name = "FM25Q08", .bustype = BUS_SPI, .manufacture_id = FUDAN_ID_NOPREFIX, @@ -6305,6 +6349,94 @@ }, { + .vendor = "Fudan", + .name = "FM25Q64", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25Q64, + .total_size = 8192, + .page_size = 256, + /* supports SFDP */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + /* 2048 * 4KB sectors */ + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + /* 256 * 32KB blocks */ + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + /* 128 * 64KB blocks */ + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + /* Full chip erase (0x60) */ + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + /* Full chip erase (0xC7) */ + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + }, + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP2_TB_BPL, /* bit6 selects size of protected blocks; TODO: SR2 */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP2_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Fudan", + .name = "FM25Q128", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25Q128, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + /* 4096 * 4KB sectors */ + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + /* 512 * 32KB blocks */ + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + /* 256 * 64KB blocks */ + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + /* Full chip erase (0x60) */ + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + /* Full chip erase (0xC7) */ + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + }, + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP2_TB_BPL, /* bit6 selects size of protected blocks; TODO: SR2 */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP2_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { .vendor = "Fujitsu", .name = "MBM29F004BC", .bustype = BUS_PARALLEL, diff --git a/include/flashchips.h b/include/flashchips.h index e4d0bca..02de72a 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -344,9 +344,12 @@ #define FUDAN_FM25F01 0x3111 #define FUDAN_FM25F02 0x3112 /* Same as FM25F02A */ #define FUDAN_FM25F04 0x3113 /* Same as FM25F04A */ +#define FUDAN_FM25Q04 0x4013 #define FUDAN_FM25Q08 0x4014 #define FUDAN_FM25Q16 0x4015 #define FUDAN_FM25Q32 0x4016 +#define FUDAN_FM25Q64 0x4017 +#define FUDAN_FM25Q128 0x4018 #define FUJITSU_ID 0x04 /* Fujitsu */ #define FUJITSU_MBM29DL400BC 0x0F -- To view, visit https://review.coreboot.org/c/flashrom/+/83969?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I88fcc2bbb9706c8adb3722da6aa0e1d2d04c3fde Gerrit-Change-Number: 83969 Gerrit-PatchSet: 3 Gerrit-Owner: Samantaz Fox <coding(a)samantaz.fr> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: ch347_spi: Add spi clock frequency selection
by ZhiYuanNJ (Code Review) 26 Aug '24

26 Aug '24

Attention is currently required from: Anastasia Klimchuk, Nicholas Chin. ZhiYuanNJ has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email ) Change subject: ch347_spi: Add spi clock frequency selection ...................................................................... Patch Set 14: (1 comment) File ch347_spi.c: https://review.coreboot.org/c/flashrom/+/82776/comment/de595cb1_572c4c96?us… : PS13, Line 291: int speed_index = 2; > Yes, I see you changed speed_index, thank you! […] Good sense， sorry for the slow response, updated. -- To view, visit https://review.coreboot.org/c/flashrom/+/82776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Gerrit-Change-Number: 82776 Gerrit-PatchSet: 14 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 26 Aug 2024 02:17:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: ZhiYuanNJ

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[M] Change in flashrom[main]: flashchips: add GD25F256F
by Victor Lim (Code Review) 26 Aug '24

26 Aug '24

Victor Lim has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/84090?usp=email ) Change subject: flashchips: add GD25F256F ...................................................................... flashchips: add GD25F256F GD25F256F: 3V 256Mbit, high performance Will send the datasheet. Tested on ch347 with erase, write, read, and protection Change-Id: Ibbbbb8a55adbcbc2ee1785782c4eb3771d50c167 Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- M flashchips.c M include/flashchips.h 2 files changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/84090/1 diff --git a/flashchips.c b/flashchips.c index 96e8760..ef8ebbf 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8010,6 +8010,60 @@ { .vendor = "GigaDevice", + .name = "GD25F256F", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25F256F, + .total_size = 32768, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2 | FEATURE_WRSR3 | FEATURE_4BA, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_5C, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */ + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "GigaDevice", .name = "GD25WQ80E", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, diff --git a/include/flashchips.h b/include/flashchips.h index be83a6f..24a1d9d 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -398,6 +398,7 @@ #define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */ #define GIGADEVICE_GD25VQ80C 0x4214 #define GIGADEVICE_GD25VQ16C 0x4215 +#define GIGADEVICE_GD25F256F 0x4319 #define GIGADEVICE_GD25LQ40 0x6013 #define GIGADEVICE_GD25LQ80 0x6014 #define GIGADEVICE_GD25LQ16 0x6015 -- To view, visit https://review.coreboot.org/c/flashrom/+/84090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ibbbbb8a55adbcbc2ee1785782c4eb3771d50c167 Gerrit-Change-Number: 84090 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com>

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[M] Change in flashrom[main]: tests: Check verify op completed in full if chip memory modified
by Peter Marheine (Code Review) 25 Aug '24

25 Aug '24

Attention is currently required from: Anastasia Klimchuk. Peter Marheine has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/84078?usp=email ) Change subject: tests: Check verify op completed in full if chip memory modified ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/84078/comment/df163ae7_0d9344df?us… : PS1, Line 18: Note: at the moment the test is not fully working, the following : write test cases fail (all erase test cases pass): Looks like it might be a fencepost error (possibly treating the upper bound of a region as exclusive rather than inclusive), since it looks like the unverified bytes might always fall at the end of a region. File tests/erase_func_algo.c: https://review.coreboot.org/c/flashrom/+/84078/comment/b54fe4e7_102f0525?us… : PS1, Line 60: uint8_t Since this is true/false, just use `bool`. https://review.coreboot.org/c/flashrom/+/84078/comment/a966e2b2_5bc432f5?us… : PS1, Line 77: == 0x1 I'd rather use implicit boolean conversion throughout (`if (g_state.was_modified[start])`). -- To view, visit https://review.coreboot.org/c/flashrom/+/84078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I3c5d55a0deb20f23f4072caac8c0dce04cc98fd4 Gerrit-Change-Number: 84078 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Sun, 25 Aug 2024 23:39:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in flashrom[main]: flashchips: add GD25B512MF and GD25R512MF
by Victor Lim (Code Review) 25 Aug '24

25 Aug '24

Victor Lim has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/84083?usp=email ) Change subject: flashchips: add GD25B512MF and GD25R512MF ...................................................................... flashchips: add GD25B512MF and GD25R512MF GD25B512MF: 3V 512Mbit, QE = 1 GD25R512MF: GD25B512MF feature + RPMC These two part share the same datasheet on the flash side. https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240412/DS-0… Tested both models on ch347 with erase, write, read, and protection. Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- M flashchips.c M include/flashchips.h 2 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/84083/1 diff --git a/flashchips.c b/flashchips.c index 5ca02c7..96e8760 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7505,6 +7505,62 @@ .decode_range = DECODE_RANGE_SPI25, }, +{ + .vendor = "GigaDevice", + .name = "GD25B512MF/GD25R512MF", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25B512MF, + .total_size = 65536, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2 | FEATURE_WRSR3 | FEATURE_4BA, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_5C, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {64 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {64 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */ + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 6, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */ + .cmp = {STATUS3, 3, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + { .vendor = "GigaDevice", .name = "GD25Q32(B)", diff --git a/include/flashchips.h b/include/flashchips.h index e4d0bca..be83a6f 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -393,6 +393,7 @@ #define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */ #define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C,and GD25Q128E, GD25B128E, GD25R128E can be distinguished by SFDP */ #define GIGADEVICE_GD25Q256D 0x4019 +#define GIGADEVICE_GD25B512MF 0x401A /* Same as GD25R512MF */ #define GIGADEVICE_GD25VQ21B 0x4212 #define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */ #define GIGADEVICE_GD25VQ80C 0x4214 -- To view, visit https://review.coreboot.org/c/flashrom/+/84083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Gerrit-Change-Number: 84083 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com>

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