Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83852?usp=email )
Change subject: flashrom.c: Rename {erase|write}_by_layout_new as the only one
......................................................................
flashrom.c: Rename {erase|write}_by_layout_new as the only one
We used to have two code paths for erase and write, so we had
{erase|write}_by_layout in two variants: *_new and *_legacy.
Now that legacy is removed, *_new can be renamed without *_new
suffix.
Change-Id: Ib21bf29e1993c4fc0516e76fde2ad283eedb50d2
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M flashrom.c
1 file changed, 2 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/52/83852/1
diff --git a/flashrom.c b/flashrom.c
index 453a2bf..01a41c4 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -1327,7 +1327,7 @@
return ret;
}
-static int erase_by_layout_new(struct flashctx *const flashctx)
+static int erase_by_layout(struct flashctx *const flashctx)
{
bool all_skipped = true;
const uint32_t flash_size = flashctx->chip->total_size * 1024;
@@ -1370,12 +1370,7 @@
return ret;
}
-static int erase_by_layout(struct flashctx *const flashctx)
-{
- return erase_by_layout_new(flashctx);
-}
-
-static int write_by_layout_new(struct flashctx *const flashctx,
+static int write_by_layout(struct flashctx *const flashctx,
void *const curcontents, const void *const newcontents,
bool *all_skipped)
{
@@ -1410,13 +1405,6 @@
return ret;
}
-static int write_by_layout(struct flashctx *const flashctx,
- uint8_t *const curcontents, const uint8_t *const newcontents,
- bool *all_skipped)
-{
- return write_by_layout_new(flashctx, curcontents, newcontents, all_skipped);
-}
-
/**
* @brief Compares the included layout regions with content from a buffer.
*
--
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Gerrit-Change-Id: Ib21bf29e1993c4fc0516e76fde2ad283eedb50d2
Gerrit-Change-Number: 83852
Gerrit-PatchSet: 1
Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>
Attention is currently required from: Aarya, Peter Marheine.
Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83846?usp=email )
Change subject: flashrom.c: Delete legacy erase and write logic
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
I was for some reasons under impression this change will need to wait until removing makefile... but actually there is no merge conflict!
So this is ready for review.
Also, I think unit tests are adequate testing for this type of change. Please tell me if you disagree.
--
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Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com>
Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org>
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Anastasia Klimchuk has uploaded a new patch set (#3). ( https://review.coreboot.org/c/flashrom/+/83846?usp=email )
Change subject: flashrom.c: Delete legacy erase and write logic
......................................................................
flashrom.c: Delete legacy erase and write logic
Current code path for erase and write has been enabled in the tree
since May 2023, which is more than 1 year ago (15 months ago),
and legacy path has been disabled since the same time.
Current logic has been officially released in v1.4.0 in July 2024.
Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M erasure_layout.c
M flashrom.c
2 files changed, 1 insertion(+), 369 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/83846/3
--
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Gerrit-Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800
Gerrit-Change-Number: 83846
Gerrit-PatchSet: 3
Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>
Anastasia Klimchuk has uploaded a new patch set (#2). ( https://review.coreboot.org/c/flashrom/+/83846?usp=email )
Change subject: flashrom.c: Delete legacy erase and write logic
......................................................................
flashrom.c: Delete legacy erase and write logic
Current code path for erase and write has been enabled in the tree
since May 2023, which is more than 1 year ago (15 months ago),
and legacy path has been disabled since the same time.
Current logic has been officially released in v1.4.0 in July 2024.
Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M flashrom.c
1 file changed, 0 insertions(+), 368 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/83846/2
--
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Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83753?usp=email )
Change subject: doc: Convert the doc for MSI JSPI1
......................................................................
doc: Convert the doc for MSI JSPI1
The doc converted from
https://wiki.flashrom.org/MSI_JSPI1
Change-Id: Idd215a3a3a4d62629803a71d360755c43c1ab599
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83753
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: David Hendricks <david.hendricks(a)gmail.com>
---
M doc/user_docs/index.rst
A doc/user_docs/msi_jspi1.rst
2 files changed, 53 insertions(+), 0 deletions(-)
Approvals:
David Hendricks: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/doc/user_docs/index.rst b/doc/user_docs/index.rst
index 6eadfa4..e03789e 100644
--- a/doc/user_docs/index.rst
+++ b/doc/user_docs/index.rst
@@ -11,4 +11,7 @@
management_engine
misc_intel
in_system
+ msi_jspi1
misc_notes
+
+.. Keep misc notes last
diff --git a/doc/user_docs/msi_jspi1.rst b/doc/user_docs/msi_jspi1.rst
new file mode 100644
index 0000000..dc20866
--- /dev/null
+++ b/doc/user_docs/msi_jspi1.rst
@@ -0,0 +1,50 @@
+=========
+MSI JSPI1
+=========
+
+JSPI1 is a 5x2 or 6x2 2.0mm pitch pin header on many MSI motherboards.
+It is used to recover from bad boot ROM images. Specifically,
+it appears to be used to connect an alternate ROM with a working image.
+Pull the #HOLD line low to deselect the onboard SPI ROM, allowing another
+SPI ROM to take its place on the bus. Pull the #WP line high to disable write-protection.
+Some boards use 1.8V flash chips, while others use 3.3V flash chips;
+Check the flash chip datasheet to determine the correct value.
+
+**JSPI1 (5x2)**
+
+======== ======== ======== ====
+name pin pin name
+======== ======== ======== ====
+VCC 1 2 VCC
+MISO 3 4 MOSI
+#SS 5 6 SCLK
+GND 7 8 GND
+#HOLD 9 10 NC
+======== ======== ======== ====
+
+**JSPI1 (6x2)**
+
+======== ======== ======== ============
+name pin pin name
+======== ======== ======== ============
+VCC 1 2 VCC
+SO 3 4 SI
+#SS 5 6 CLK
+GND 7 8 GND
+NC 9 10 NC (no pin)
+#WP 11 12 #HOLD
+======== ======== ======== ============
+
+======== =====================================
+name function
+======== =====================================
+VCC Voltage (See flash chip datasheet)
+MISO SPI Master In/Slave Out
+MOSI SPI Master Out/Slave In
+#SS SPI Slave (Chip) Select (active low)
+SCLK SPI Clock
+GND ground/common
+#HOLD SPI hold (active low)
+#WP SPI write-protect (active low)
+NC Not Connected (or no pin)
+======== =====================================
--
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Gerrit-Change-Number: 83753
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/83834?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: tree: Retype variable `is_laptop` to enum
......................................................................
tree: Retype variable `is_laptop` to enum
Use enum instead of integer for the variable `is_laptop`.
Change-Id: I47b7611a08bdf9992131cab57ee386fd59d147d3
Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com>
---
M board_enable.c
M dmi.c
M include/programmer.h
M internal.c
4 files changed, 38 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/83834/3
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Gerrit-Change-Id: I47b7611a08bdf9992131cab57ee386fd59d147d3
Gerrit-Change-Number: 83834
Gerrit-PatchSet: 3
Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>