August 2024 - flashrom-gerrit - mail.coreboot.org

[L] Change in flashrom[main]: doc: Add overview doc for user_docs
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83584?usp=email ) Change subject: doc: Add overview doc for user_docs ...................................................................... Patch Set 2: (1 comment) File doc/user_docs/overview.rst: https://review.coreboot.org/c/flashrom/+/83584/comment/c35a2376_5339398b?us… : PS1, Line 188: :doc:`in-system` > the doc is in CB:83451 Done -- To view, visit https://review.coreboot.org/c/flashrom/+/83584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I93107d6b5530c301dd90f7177758632d9d1810eb Gerrit-Change-Number: 83584 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Aug 2024 08:43:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: doc: Add doc for buspirate programmer
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83471?usp=email ) Change subject: doc: Add doc for buspirate programmer ...................................................................... doc: Add doc for buspirate programmer Doc migrated from the wiki page: https://wiki.flashrom.org/Bus_Pirate Change-Id: I5a57f08ea3fce0c78d73aa61b85ff7b0cff450b8 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83471 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Reguera Garcia (Dreg) <regueragarciadavid(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- A doc/supported_hw/supported_prog/Buspirate_v3_back.jpg A doc/supported_hw/supported_prog/Buspirate_v3_front.jpg A doc/supported_hw/supported_prog/Lycom-pe115-flashrom-buspirate-2.jpg A doc/supported_hw/supported_prog/buspirate.rst M doc/supported_hw/supported_prog/index.rst 5 files changed, 79 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved David Reguera Garcia (Dreg): Looks good to me, approved diff --git a/doc/supported_hw/supported_prog/Buspirate_v3_back.jpg b/doc/supported_hw/supported_prog/Buspirate_v3_back.jpg new file mode 100644 index 0000000..3afb974 --- /dev/null +++ b/doc/supported_hw/supported_prog/Buspirate_v3_back.jpg Binary files differ diff --git a/doc/supported_hw/supported_prog/Buspirate_v3_front.jpg b/doc/supported_hw/supported_prog/Buspirate_v3_front.jpg new file mode 100644 index 0000000..3c4fa9c --- /dev/null +++ b/doc/supported_hw/supported_prog/Buspirate_v3_front.jpg Binary files differ diff --git a/doc/supported_hw/supported_prog/Lycom-pe115-flashrom-buspirate-2.jpg b/doc/supported_hw/supported_prog/Lycom-pe115-flashrom-buspirate-2.jpg new file mode 100644 index 0000000..5962fa9 --- /dev/null +++ b/doc/supported_hw/supported_prog/Lycom-pe115-flashrom-buspirate-2.jpg Binary files differ diff --git a/doc/supported_hw/supported_prog/buspirate.rst b/doc/supported_hw/supported_prog/buspirate.rst new file mode 100644 index 0000000..3d06470 --- /dev/null +++ b/doc/supported_hw/supported_prog/buspirate.rst @@ -0,0 +1,78 @@ +========== +Bus Pirate +========== + +The `Bus Pirate <http://dangerousprototypes.com/docs/Bus_Pirate>`_ is an open source design +for a multi-purpose chip-level serial protocol transceiver and debugger. +flashrom supports the Bus Pirate for `SPI programming <http://dangerousprototypes.com/docs/SPI>`_. +It also has `SPI sniffing <http://dangerousprototypes.com/docs/Bus_Pirate_binary_SPI_sniffer_utility>`_ +functionality, which may come in useful for analysing chip or programmer behaviour. + +They are available for around US$30 from various sources. + +Connections +=========== + +The table below shows how a typical SPI flash chip (sitting in the center of the table) +needs to be connected (NB: not all flash chips feature all of the pins below, but in general +you should always connect all input pins of ICs to some defined potential (usually GND or VCC), +ideally with a pull-up/down resistor in between). Most SPI flash chips require a 3.3V supply voltage, +but there exist some models that use e.g. 1.8V. Make sure the device in question is compatible +before connecting any wires. + +*NB: Some rather rare SPI flash chips (e.g. Atmel AT45DB series) have a completely different layout, please beware.* + ++----------------------+------------+------+---------------------------------+------+------------+-----------------------------+ +| Description | Bus Pirate | Dir. | Flash chip | Dir. | Bus Pirate | Description | ++======================+============+======+===+===========+=============+===+======+============+=============================+ +| (not) Chip Select | CS | → | 1 | /CS | VCC | 8 | ← | +3.3v | Supply | ++----------------------+------------+------+---+-----------+-------------+---+------+------------+-----------------------------+ +| Master In, Slave Out | MISO | ← | 2 | DO (IO1) | /HOLD (IO3) | 7 | ← | +3.3v | (not) hold (see datasheets) | ++----------------------+------------+------+---+-----------+-------------+---+------+------------+-----------------------------+ +| (not) Write Protect | +3.3v | → | 3 | /WP (IO2) | CLK | 6 | ← | CLK | The SPI clock | ++----------------------+------------+------+---+-----------+-------------+---+------+------------+-----------------------------+ +| Ground | GND | → | 4 | GND | DI (IO0) | 5 | ← | MOSI | Master Out, Slave In | ++----------------------+------------+------+---+-----------+-------------+---+------+------------+-----------------------------+ + +Usage +========= + +:: + + $ flashrom -p buspirate_spi:dev=/dev/device,spispeed=frequency + +Example:: + + $ flashrom -p buspirate_spi:dev=/dev/ttyUSB0,spispeed=1M + +Troubleshooting +=============== + +In case of problems probing the chip with flashrom - especially when connecting chips +still soldered in a system - please take a look at the doc :doc:`/user_docs/in_system`. In-system programming is often possible +**only as long as no other devices on the SPI bus are trying to access the device**. + +Speedup +========= + +A beta firmware build exists, to speed up the buspirate. +`See this post on dangerousprototypes.com <http://dangerousprototypes.com/forum/viewtopic.php?f=40&t=3864&start=15#p41…>`_ + +See also: http://dangerousprototypes.com/docs/Bus_Pirate#Firmware_upgrades + +Images +========== + +Bus Pirate v3, front. + +.. image:: Buspirate_v3_front.jpg + +Bus Pirate v3, back. + +.. image:: Buspirate_v3_back.jpg + +Recovering a bricked Lycom PE-115 88SE8123 PCIe to SATA adapter using flashrom and a Bus Pirate - power to the +PE-115 is supplied by a PC. The test probes of the bus pirate are attached directly to the SOIC Atmel AT26F004 SPI flash chip. +The other test clip is connected to GND on another device for convenience (easier than getting yet another clip onto a SOIC device). + +.. image:: Lycom-pe115-flashrom-buspirate-2.jpg diff --git a/doc/supported_hw/supported_prog/index.rst b/doc/supported_hw/supported_prog/index.rst index 130ac20..ec96b9f 100644 --- a/doc/supported_hw/supported_prog/index.rst +++ b/doc/supported_hw/supported_prog/index.rst @@ -15,5 +15,6 @@ .. toctree:: :maxdepth: 1 + buspirate dummyflasher serprog/index -- To view, visit https://review.coreboot.org/c/flashrom/+/83471?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I5a57f08ea3fce0c78d73aa61b85ff7b0cff450b8 Gerrit-Change-Number: 83471 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Reguera Garcia (Dreg) <regueragarciadavid(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: doc: Add doc for in-system programming
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83451?usp=email ) Change subject: doc: Add doc for in-system programming ...................................................................... doc: Add doc for in-system programming The page on wiki is here: https://wiki.flashrom.org/ISP Change-Id: If4752f0f02ae973b3d832f42166de643d95c9f97 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83451 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Alexander Goncharov <chat(a)joursoir.net> --- A doc/user_docs/1200px-DIP_socket_as_SOIC_clip.jpg A doc/user_docs/Pomona_5250_soic8.jpg A doc/user_docs/in_system.rst M doc/user_docs/index.rst 4 files changed, 46 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Alexander Goncharov: Looks good to me, approved diff --git a/doc/user_docs/1200px-DIP_socket_as_SOIC_clip.jpg b/doc/user_docs/1200px-DIP_socket_as_SOIC_clip.jpg new file mode 100644 index 0000000..c3db692 --- /dev/null +++ b/doc/user_docs/1200px-DIP_socket_as_SOIC_clip.jpg Binary files differ diff --git a/doc/user_docs/Pomona_5250_soic8.jpg b/doc/user_docs/Pomona_5250_soic8.jpg new file mode 100644 index 0000000..83f8c3e --- /dev/null +++ b/doc/user_docs/Pomona_5250_soic8.jpg Binary files differ diff --git a/doc/user_docs/in_system.rst b/doc/user_docs/in_system.rst new file mode 100644 index 0000000..84716d3 --- /dev/null +++ b/doc/user_docs/in_system.rst @@ -0,0 +1,45 @@ +===================== +In-System Programming +===================== + +**In-System Programming** (ISP) sometimes also called **in situ programming** is used to describe +the procedure of writing a flash chip while it is (already/still) attached to the circuit +it is to be used with. Of course any normal "BIOS flash" procedure is a kind of ISP +but when we refer to ISP we usually mean something different: programming a flash chip by external means +while it is mounted on a motherboard. + +This is usually done with SPI chips only. Some mainboards have a special header for this +(often named "ISP", "ISP1", or "SPI") and there should be no problem with accessing the chip +then as long as the wires are not too long. + +If there is no special header then using a special SO(IC) clip is an easy and reliable way +to attach an external programmer. They are produced by different vendors (e.g. Pomona, 3M) +and are available from many distributors (e.g. Distrelec) for 20-50$/€. + +Problems +======== + +* Check the other potential problems (:doc:`misc_notes`) with other types of programming setups first. +* The SPI bus is not isolated enough. Often parts of the chipset are powered on partially + (by the voltage supplied via the Vcc pin of the flash chip). In that case + disconnect Vcc from the programmer and power it with its normal PSU and: + + * Try powering up the board normally and holding it in reset (e.g. use a jumper instead of the reset push button). + * Some chipsets (e.g. Intel ICHs/PCHs) have edge triggered resets. In this case holding them in reset will not work. + This is especially a problem with Intel chipsets because they contain an EC (named ME by Intel, see :doc:`management_engine`), + which uses the flash (r/w!). In this case you can trigger the reset line in short intervals. + For example by connecting it to the chip select (CS) line of the SPI bus or a dedicated clock signal from the programmer. + This should not be too fast though! Reset lines usually require pulses with a minimum duration. + * On some boards, you can try disconnecting the ATX12V header (yellow/black wires only) from the motherboard, + or even remove the CPU or RAM - if the programmer supports SPI sniffing, you may be able to verify that the there is no SPI traffic. + +Images +======== + +Pomona 8-pin SOIC clip with attached jumper wires. + +.. image:: Pomona_5250_soic8.jpg + +A cheap, but very fragile alternative: DIP socket as clip + +.. image:: 1200px-DIP_socket_as_SOIC_clip.jpg diff --git a/doc/user_docs/index.rst b/doc/user_docs/index.rst index 960659e..3ca928a 100644 --- a/doc/user_docs/index.rst +++ b/doc/user_docs/index.rst @@ -9,4 +9,5 @@ chromebooks management_engine misc_intel + in_system misc_notes -- To view, visit https://review.coreboot.org/c/flashrom/+/83451?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If4752f0f02ae973b3d832f42166de643d95c9f97 Gerrit-Change-Number: 83451 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: doc: Add page with misc notes and advice
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83450?usp=email ) Change subject: doc: Add page with misc notes and advice ...................................................................... doc: Add page with misc notes and advice This page is a combination of info from the following pages: https://wiki.flashrom.org/Common_problems https://wiki.flashrom.org/Connections https://wiki.flashrom.org/FAQ https://wiki.flashrom.org/Random_notes https://wiki.flashrom.org/Live_CD Change-Id: I538f31765576584760524cd8b06cbf5bce191bde Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83450 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M doc/user_docs/index.rst A doc/user_docs/misc_notes.rst 2 files changed, 150 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/doc/user_docs/index.rst b/doc/user_docs/index.rst index b61567a..960659e 100644 --- a/doc/user_docs/index.rst +++ b/doc/user_docs/index.rst @@ -9,3 +9,4 @@ chromebooks management_engine misc_intel + misc_notes diff --git a/doc/user_docs/misc_notes.rst b/doc/user_docs/misc_notes.rst new file mode 100644 index 0000000..fcb1700 --- /dev/null +++ b/doc/user_docs/misc_notes.rst @@ -0,0 +1,149 @@ +===================== +Misc notes and advice +===================== + +This document contains miscellaneous and unstructured (and mostly, legacy) notes and advice about using flashrom. + +Command set tricks for parallel and LPC chips +============================================= + +This is only mentioned in very few datasheets, but it applies to some parallel (and some LPC) chips. + +Upper address bits of commands are ignored if they are not mentioned explicitly. If a datasheet specifies the following sequence:: + + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x90, bios + 0x555); + +then it is quite likely the following sequence will work as well:: + + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); + +However, if the chip datasheet specifies addresses like ``0x5555``, you can't shorten them to ``0x555``. + +To summarize, replacing short addresses with long addresses usually works, but the other way round usually fails. + +flashrom doesn't work on my board, what can I do? +================================================= + +* First of all, check if your chipset, ROM chip, and mainboard are supported + (see :doc:`/supported_hw/index`). +* If your board has a jumper for BIOS flash protection (check the manual), disable it. +* Should your BIOS menu have a BIOS flash protection option, disable it. +* If you run flashrom on Linux and see messages about ``/dev/mem``, see next section. +* If you run flashrom on OpenBSD, you might need to obtain raw access permission by setting + ``securelevel = -1`` in ``/etc/rc.securelevel`` and rebooting, or rebooting into single user mode. + +What can I do about /dev/mem errors? +==================================== + +* If flashrom tells you ``/dev/mem mmap failed: Operation not permitted``: + + * Most common at the time of writing is a Linux kernel option, ``CONFIG_IO_STRICT_DEVMEM``, + that prevents even the root user from accessing hardware from user-space if the resource is unknown + to the kernel or a conflicting kernel driver reserved it. On Intel systems, this is most often ``lpc_ich``, + so ``modprobe -r lpc_ich`` can help. A more invasive solution is to try again after rebooting + with ``iomem=relaxed`` in the kernel command line. + + * Some systems with incorrect memory reservations (e.g. E820 map) may have the same problem + even with ``CONFIG_STRICT_DEVMEM``. In that case ``iomem=relaxed`` in the kernel command line may help too. + +* If it tells you ``/dev/mem mmap failed: Resource temporarily unavailable``: + + * This may be an issue with PAT (e.g. if the memory flashrom tries to map is already mapped + in an incompatible mode). Try again after rebooting with nopat in the kernel command line. + +* If you see this message ``Can't mmap memory using /dev/mem: Invalid argument``: + + * Your flashrom is very old, better update it. If the issue persists, try the kernel options mentioned above. + +* Generally, if your version of flashrom is very old, an update might help. + Flashrom has less strict requirements now and works on more systems without having to change the kernel. + +Connections +=========== + +Using In-System programming requires some means to connect the external programmer to the flash chip. + +Note that some external flashers (like the Openmoko debug board) lack a connector, +so they do requires some soldering to be used. Some other don't. For instance the buspirate has a pin connector on it. + +Programmer <-> Removable chip connection +---------------------------------------- + +A breadboard can be used to connect Dual in-line 8 pins chips to the programmer, as they they fit well into it. + +Programmer <-> Clip connection +------------------------------ + +If your programmer has a pin connector, and that you want to avoid soldering, you can use +**Short** `Jump Wires <https://en.wikipedia.org/wiki/Jump_wire>`_ to connect it to a clip. +They usually can be found on some electronic shops. + +Other issues +------------- + +* Wires length and connection quality: Long wires, and bad connection can create some issues, so avoid them. + + * The maximum wires length is very dependent on your setup, so try to have the shortest wires possible. + * If you can't avoid long wires and if you're flash chip is SPI, then lowering the SPI clock could make + it work in some cases. Many programmers do support such option (Called spispeed with most of them, or divisor with ft2232_spi). + +* When soldering wires, the wire tend to break near the soldering point. To avoid such issue, + you have to prevent the wires from bending near the soldering point. + To do that `Heat-shrink_tubing <https://en.wikipedia.org/wiki/Heat-shrink_tubing>`_ or similar methods can be used. + +Common problems +=============== + +The following describes problems commonly found when trying to access flash chips in systems +that are not designed properly for this job, e.g. ad-hoc setups to flash in-system +(TODO add a doc for in-system-specific problems). + +Symptoms indicating you may have at least one of these are for example inconsistent reads or probing results. +This happens basically because the analog electrical waveforms representing the digital information +get too distorted to by interpreted correctly all the time. Depending on the cause different steps can be tried. + +* Not all input pins are connected to the correct voltage level/output pin of the programmer. + Always connect all input pins of ICs! + +* The easiest thing to try is lowering the (SPI) clock frequency if your programmer supports it. + That way the waveforms have more time to settle before being sampled by the receiver which might be enough. + Depending on the design of the driver and receiver as well as the actual communication path + this might not change anything as well. + +* Wires are too long. Shortening them to a few cm (i.e. < 20, the lesser the better) might help. + +* The impedances of the wires/traces do not match the impedances of the input pins + (of either the circuit/chip on the mainboard or the external programmer). + Try using shorter wires, adding small (<100 Ohm) series resistors or parallel capacitors (<20pF) + as near as possible to the input pins (this includes also the MISO line which ends near the programmer)\ + and/or ask someone who has experience with high frequency electronics. + +* The supply voltage of the flash chip is not stable enough. Try adding a 0.1 µF - 1 µF (ceramic) capacitor + between the flash chip's VCC and GND pins as near as possible to the chip. + +Live CD +========= + +A Live CD containing flashrom provides a user with a stable work environment to read, write and verify a flash device on any supported hardware. + +It can help avoid Linux installation issues, which can be a hassle for some users. + +flashrom is already shipped in some of the Live CDs, see below. *Please note, some of these ship very old versions of flashrom*. + +* `SystemRescueCd <http://www.sysresccd.org/>`_ has been including flashrom since about version 2.5.1. + +* `grml <http://grml.org/>`_ + + * Note: You need the full grml ISO, "small" (and "medium") ISOs do not contain flashrom. + * Note: Some releases (e.g. 2011.12) did not contain flashrom. + +* `Parted Magic <http://partedmagic.com/>`_ + +* `Hiren's BootCD <http://www.hirensbootcd.org/>`_ + + * When you select "Linux based rescue environment (Parted Magic 6.7)" and then "Live with default settings", + you have access to a system which has flashrom. -- To view, visit https://review.coreboot.org/c/flashrom/+/83450?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I538f31765576584760524cd8b06cbf5bce191bde Gerrit-Change-Number: 83450 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in flashrom[main]: doc: Add manpage item for nicintel_spi
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Attention is currently required from: Idwer Vollering. Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83751?usp=email ) Change subject: doc: Add manpage item for nicintel_spi ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hello Idwer! You are the author of nicintel page on wiki (and the programmer nicintel_spi), maybe you can review this patch? That page is really small and it wasn't referenced from any other page (probably by accident, but still). So I thought it can be just a little section on nicintel_spi to the manpage. If you agree, you can vote +1. If at some point you want to expand the documentation about nicintel_spi, or create a separate longer page, it's not a problem, doc can be added any time. Thank you! -- To view, visit https://review.coreboot.org/c/flashrom/+/83751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I139065611c68c0fa0a675fe49a6f8bc20e9057f7 Gerrit-Change-Number: 83751 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Comment-Date: Sat, 03 Aug 2024 07:40:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in flashrom[main]: flashchips: add GD25LF256F
by Anastasia Klimchuk (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/83717?usp=email ) Change subject: flashchips: add GD25LF256F ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/83717/comment/3cd44264_7a6a059b?us… : PS1, Line 13: I will have to email you the datasheet. Yes, that would be great! I will wait for you to send me a datasheet. -- To view, visit https://review.coreboot.org/c/flashrom/+/83717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I21a71606476e823faa38a7920aa2b10e25d68d26 Gerrit-Change-Number: 83717 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 02 Aug 2024 12:33:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in flashrom[main]: doc: Convert the doc for MSI JSPI1
by Anastasia Klimchuk (Code Review) 02 Aug '24

02 Aug '24

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83753?usp=email ) Change subject: doc: Convert the doc for MSI JSPI1 ...................................................................... doc: Convert the doc for MSI JSPI1 The doc converted from https://wiki.flashrom.org/MSI_JSPI1 Change-Id: Idd215a3a3a4d62629803a71d360755c43c1ab599 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M doc/user_docs/index.rst A doc/user_docs/msi_jspi1.rst 2 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/53/83753/1 diff --git a/doc/user_docs/index.rst b/doc/user_docs/index.rst index b61567a..6756d9e 100644 --- a/doc/user_docs/index.rst +++ b/doc/user_docs/index.rst @@ -9,3 +9,4 @@ chromebooks management_engine misc_intel + msi_jspi1 diff --git a/doc/user_docs/msi_jspi1.rst b/doc/user_docs/msi_jspi1.rst new file mode 100644 index 0000000..dc20866 --- /dev/null +++ b/doc/user_docs/msi_jspi1.rst @@ -0,0 +1,50 @@ +========= +MSI JSPI1 +========= + +JSPI1 is a 5x2 or 6x2 2.0mm pitch pin header on many MSI motherboards. +It is used to recover from bad boot ROM images. Specifically, +it appears to be used to connect an alternate ROM with a working image. +Pull the #HOLD line low to deselect the onboard SPI ROM, allowing another +SPI ROM to take its place on the bus. Pull the #WP line high to disable write-protection. +Some boards use 1.8V flash chips, while others use 3.3V flash chips; +Check the flash chip datasheet to determine the correct value. + +**JSPI1 (5x2)** + +======== ======== ======== ==== +name pin pin name +======== ======== ======== ==== +VCC 1 2 VCC +MISO 3 4 MOSI +#SS 5 6 SCLK +GND 7 8 GND +#HOLD 9 10 NC +======== ======== ======== ==== + +**JSPI1 (6x2)** + +======== ======== ======== ============ +name pin pin name +======== ======== ======== ============ +VCC 1 2 VCC +SO 3 4 SI +#SS 5 6 CLK +GND 7 8 GND +NC 9 10 NC (no pin) +#WP 11 12 #HOLD +======== ======== ======== ============ + +======== ===================================== +name function +======== ===================================== +VCC Voltage (See flash chip datasheet) +MISO SPI Master In/Slave Out +MOSI SPI Master Out/Slave In +#SS SPI Slave (Chip) Select (active low) +SCLK SPI Clock +GND ground/common +#HOLD SPI hold (active low) +#WP SPI write-protect (active low) +NC Not Connected (or no pin) +======== ===================================== -- To view, visit https://review.coreboot.org/c/flashrom/+/83753?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Idd215a3a3a4d62629803a71d360755c43c1ab599 Gerrit-Change-Number: 83753 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>

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[XS] Change in flashrom[main]: doc: Add manpage item for nicintel_spi
by Anastasia Klimchuk (Code Review) 02 Aug '24

02 Aug '24

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83751?usp=email ) Change subject: doc: Add manpage item for nicintel_spi ...................................................................... doc: Add manpage item for nicintel_spi The existing page on old wiki is very small and fits into a manpage item: https://wiki.flashrom.org/NICIntel Change-Id: I139065611c68c0fa0a675fe49a6f8bc20e9057f7 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M doc/classic_cli_manpage.rst 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/51/83751/1 diff --git a/doc/classic_cli_manpage.rst b/doc/classic_cli_manpage.rst index d8380c7..36dd125 100644 --- a/doc/classic_cli_manpage.rst +++ b/doc/classic_cli_manpage.rst @@ -664,6 +664,11 @@ Please note that the small number of address lines connected to the chip may make accessing large chips impossible. The maximum supported chip size is 128KB. +nicintel_spi programmer +^^^^^^^^^^^^^^^^^^^^^^^ + +Programmer for SPI flash ROMs on Intel Gigabit network cards. Tested on 32-bit hardware/PCI only. + nicintel_eeprom programmer ^^^^^^^^^^^^^^^^^^^^^^^^^^ -- To view, visit https://review.coreboot.org/c/flashrom/+/83751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I139065611c68c0fa0a675fe49a6f8bc20e9057f7 Gerrit-Change-Number: 83751 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: doc: Add doc for buspirate programmer
by David Reguera Garcia (Dreg) (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Anastasia Klimchuk. David Reguera Garcia (Dreg) has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83471?usp=email ) Change subject: doc: Add doc for buspirate programmer ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > David, I have added you to maintainers and you are now a member in "flashrom reviewers" group! Welco […] Confirmed! I can vote +2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83471?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I5a57f08ea3fce0c78d73aa61b85ff7b0cff450b8 Gerrit-Change-Number: 83471 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Reguera Garcia (Dreg) <regueragarciadavid(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Aug 2024 06:01:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: doc: Add doc for buspirate programmer
by David Reguera Garcia (Dreg) (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Anastasia Klimchuk. David Reguera Garcia (Dreg) has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83471?usp=email ) Change subject: doc: Add doc for buspirate programmer ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83471?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I5a57f08ea3fce0c78d73aa61b85ff7b0cff450b8 Gerrit-Change-Number: 83471 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Reguera Garcia (Dreg) <regueragarciadavid(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Aug 2024 05:56:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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