May 2024 - flashrom-gerrit - mail.coreboot.org

[XS] Change in flashrom[main]: flashrom: Don't throw around "delay 1 second" so lightly
by Peter Marheine (Code Review) 06 May '24

06 May '24

Attention is currently required from: Anastasia Klimchuk, Brian Norris. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/80807?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: flashrom: Don't throw around "delay 1 second" so lightly ...................................................................... Patch Set 5: (1 comment) Patchset: PS1: > > I think that recommendation should be captured in some kind of changelog so there's "real" documen […] Angel's suggestion (on the list) to continue using the delay for `!BUS_NONSPI` seems like a reasonable compromise between safety and wastefulness (and should work for all the programmers that ChromeOS cares about). Do you plan to make that change? -- To view, visit https://review.coreboot.org/c/flashrom/+/80807?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie09651fede3f9f03425244c94a2da8bae00315fc Gerrit-Change-Number: 80807 Gerrit-PatchSet: 5 Gerrit-Owner: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Brian Norris <briannorris(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 06 May 2024 03:57:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Brian Norris <briannorris(a)chromium.org> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in flashrom[main]: Bug fix: Fix CH347T PID, interface, and clock settings errors
by ZhiYuanNJ (Code Review) 06 May '24

06 May '24

Attention is currently required from: Nicholas Chin. Hello Nicholas Chin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/82193?usp=email to look at the new patch set (#2). Change subject: Bug fix: Fix CH347T PID, interface, and clock settings errors ...................................................................... Bug fix: Fix CH347T PID, interface, and clock settings errors Add functionality : Add support for CH347F. The latest package with F as 347, compared to T, does not require active mode switching and can simultaneously meet communication requirements such as USB to SPI/I2C CH347 introduce is available at the following URL: https://www.wch-ic.com/products/CH347.html?from=search&wd=eyJpdiI6Im4zdVRJd… Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Signed-off-by: ZhiYuanNJ <871238103(a)qq.com> --- M ch347_spi.c 1 file changed, 84 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/82193/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/82193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Gerrit-Change-Number: 82193 Gerrit-PatchSet: 2 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[main]: Bug fix: Fix CH347T PID, interface, and clock settings errors Add fun...
by ZhiYuanNJ (Code Review) 06 May '24

06 May '24

ZhiYuanNJ has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/82193?usp=email ) Change subject: Bug fix: Fix CH347T PID, interface, and clock settings errors Add functionality : Add support for CH347F. The latest package with F as 347, compared to T, does not require active mode switching and can simultaneously meet communication requirements such as USB to SPI/I2C H347 introduce is available at the following URL: https://www.wch-ic.com/products/CH347.html?from=search&wd=eyJpdiI6Im4zdVRJd… ...................................................................... Bug fix: Fix CH347T PID, interface, and clock settings errors Add functionality : Add support for CH347F. The latest package with F as 347, compared to T, does not require active mode switching and can simultaneously meet communication requirements such as USB to SPI/I2C H347 introduce is available at the following URL: https://www.wch-ic.com/products/CH347.html?from=search&wd=eyJpdiI6Im4zdVRJd… Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Signed-off-by: ZhiYuanNJ <871238103(a)qq.com> --- M ch347_spi.c 1 file changed, 84 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/82193/1 diff --git a/ch347_spi.c b/ch347_spi.c index 570e25b..33caa68 100644 --- a/ch347_spi.c +++ b/ch347_spi.c @@ -7,7 +7,25 @@ * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * + * + * CH347 is a high-speed USB bus converter chip that provides UART, I2C + * and SPI synchronous serial ports and JTAG interface through USB bus. + * + * The SPI interface by CH347 can supports transmission frequency + * configuration up to 60MHz. + * + * The USB2.0 to spi scheme based on CH347 can be used to build + * customized USB high-speed spi debugger and other products. + * + * _____________ + * | |____SPI (MISO,MOSI,SCK,CSC0,CSC1) + * USB__| CH347T/F | + * |_____________|____(UART/I2C/JTAG/SWD/GPIO) + * ______|______ + * | | + * | 8 MHz XTAL | + * |_____________| + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the @@ -36,8 +54,8 @@ #define WRITE_EP 0x06 #define READ_EP 0x86 -#define MODE_1_IFACE 2 -#define MODE_2_IFACE 1 +#define CH347T_IFACE 2 +#define CH347F_IFACE 4 /* The USB descriptor says the max transfer size is 512 bytes, but the * vendor driver only seems to transfer a maximum of 510 bytes at once, @@ -46,22 +64,46 @@ #define CH347_PACKET_SIZE 510 #define CH347_MAX_DATA_LEN (CH347_PACKET_SIZE - 3) +struct device_speeds { + const char *name; + const int speed; +}; + struct ch347_spi_data { struct libusb_device_handle *handle; + int interface; }; /* TODO: Add support for HID mode */ static const struct dev_entry devs_ch347_spi[] = { - {0x1A86, 0x55DB, OK, "QinHeng Electronics", "USB To UART+SPI+I2C"}, + {0x1A86, 0x55DD, OK, "QinHeng Electronics", "USB To UART+SPI+I2C"}, //CH347T + {0x1A86, 0x55DE, OK, "QinHeng Electronics", "USB To UART+SPI+I2C"}, //CH347F {0} }; +static const struct device_speeds spispeeds[] = { + {"60M", 0x0}, + {"30M", 0x1}, + {"15M", 0x2}, + {"7.5M", 0x3}, + {"3.75M", 0x4}, + {"1.875M", 0x5}, + {"937.5K", 0x6}, + {"468.75K", 0x7}, + {NULL, 0x0} +}; + +static int ch347_interface[] = { + 2, //CH347T interface number + 4, //CH347F interface number +}; + static int ch347_spi_shutdown(void *data) { struct ch347_spi_data *ch347_data = data; /* TODO: Set this depending on the mode */ - int spi_interface = MODE_1_IFACE; + int spi_interface = ch347_data->interface; libusb_release_interface(ch347_data->handle, spi_interface); libusb_attach_kernel_driver(ch347_data->handle, spi_interface); libusb_close(ch347_data->handle); @@ -215,6 +257,8 @@ /* Not sure what these two bytes do, but the vendor * drivers seem to unconditionally set these values */ + [3] = 0, + [4] = 0, [5] = 4, [6] = 1, /* Clock polarity: bit 1 */ @@ -262,6 +306,11 @@ /* Largely copied from ch341a_spi.c */ static int ch347_spi_init(const struct programmer_cfg *cfg) { + char *arg; + uint16_t vid = devs_ch347_spi[0].vendor_id; + uint16_t pid = 0; + int index = 0; + int spispeed = 0x0; //defaulet 60M SPI struct ch347_spi_data *ch347_data = calloc(1, sizeof(*ch347_data)); if (!ch347_data) { msg_perr("Could not allocate space for SPI data\n"); @@ -281,26 +330,28 @@ #else libusb_set_option(NULL, LIBUSB_OPTION_LOG_LEVEL, LIBUSB_LOG_LEVEL_INFO); #endif - - uint16_t vid = devs_ch347_spi[0].vendor_id; - uint16_t pid = devs_ch347_spi[0].device_id; - ch347_data->handle = libusb_open_device_with_vid_pid(NULL, vid, pid); - if (ch347_data->handle == NULL) { - msg_perr("Couldn't open device %04x:%04x.\n", vid, pid); - free(ch347_data); - return 1; + while (devs_ch347_spi[index].vendor_id != 0) { + vid = devs_ch347_spi[index].vendor_id; + pid = devs_ch347_spi[index].device_id; + ch347_data->handle = libusb_open_device_with_vid_pid(NULL, vid, pid); + if (ch347_data->handle) { + ch347_data->interface = ch347_interface[index]; + break; + } + index++; } + if (!ch347_data->handle){ + msg_perr("Couldn't open device %04x:%04x.\n", vid, pid); + free(ch347_data); + return 1; + } - /* TODO: set based on mode */ - /* Mode 1 uses interface 2 for the SPI interface */ - int spi_interface = MODE_1_IFACE; - - ret = libusb_detach_kernel_driver(ch347_data->handle, spi_interface); + ret = libusb_detach_kernel_driver(ch347_data->handle, ch347_data->interface); if (ret != 0 && ret != LIBUSB_ERROR_NOT_FOUND) msg_pwarn("Cannot detach the existing USB driver. Claiming the interface may fail. %s\n", libusb_error_name(ret)); - ret = libusb_claim_interface(ch347_data->handle, spi_interface); + ret = libusb_claim_interface(ch347_data->handle, ch347_data->interface); if (ret != 0) { msg_perr("Failed to claim interface 2: '%s'\n", libusb_error_name(ret)); goto error_exit; @@ -325,11 +376,22 @@ (desc.bcdDevice >> 0) & 0x000F); /* TODO: add programmer cfg for things like CS pin and divisor */ - if (ch347_spi_config(ch347_data, 2) < 0) + arg = extract_programmer_param_str(cfg, "spispeed"); + if (arg) { + for (index = 0; spispeeds[index].name; index++) { + if (!strncasecmp(spispeeds[index].name, arg, strlen(spispeeds[index].name))) { + spispeed = spispeeds[index].speed; + break; + } + } + } + if (!spispeeds[index].name || !arg) + msg_perr("Invalid SPI speed, using defaul(60M clock spi).\n"); + free(arg); + /* TODO: add programmer cfg for things like CS pin and divisor */ + if (ch347_spi_config(ch347_data, spispeed) < 0) goto error_exit; - return register_spi_master(&spi_master_ch347_spi, ch347_data); - error_exit: ch347_spi_shutdown(ch347_data); return 1; -- To view, visit https://review.coreboot.org/c/flashrom/+/82193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Gerrit-Change-Number: 82193 Gerrit-PatchSet: 1 Gerrit-Owner: ZhiYuanNJ Gerrit-MessageType: newchange

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[S] Change in flashrom[main]: Make sleep threshold for delays configurable
by Peter Marheine (Code Review) 06 May '24

06 May '24

Attention is currently required from: Anastasia Klimchuk, Thomas Heijligen. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/81606?usp=email ) Change subject: Make sleep threshold for delays configurable ...................................................................... Patch Set 5: (1 comment) File udelay_dos.c: https://review.coreboot.org/c/flashrom/+/81606/comment/484e9882_4ff2d9b5 : PS4, Line 161: CONFIG_DELAY_MINIMUM_SLEEP_US > probably also needs the same `static const` trick? Yup! I also had another go at actually using DJGPP which revealed a shortcoming with the current DOS delay code (see parent changes), but I can now confirm that the DOS delay code does compile. -- To view, visit https://review.coreboot.org/c/flashrom/+/81606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ida96e0816ac914ed69d6fd82ad90ebe89cdef1cc Gerrit-Change-Number: 81606 Gerrit-PatchSet: 5 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 06 May 2024 03:53:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in flashrom[main]: flashchips: Add support for GigaDevice GD25LR256E, GD251R512ME
by Peter Marheine (Code Review) 06 May '24

06 May '24

Attention is currently required from: Angel Pons, Martin L Roth, Martin Roth, Raj Astekar, Ravishankar Sarawadi, Wonkyu Kim. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58025?usp=email ) Change subject: flashchips: Add support for GigaDevice GD25LR256E, GD251R512ME ...................................................................... Patch Set 8: Code-Review+1 (1 comment) Patchset: PS8: Does this change need anything else? There was interest in support for this chip on the mailing list: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/7U7K… -- To view, visit https://review.coreboot.org/c/flashrom/+/58025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I2fe6bc1219cd1ee19b93caabab69de938cfc44b0 Gerrit-Change-Number: 58025 Gerrit-PatchSet: 8 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Mon, 06 May 2024 03:51:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in flashrom[main]: dos/meson: add a hint for setting sys_root
by Peter Marheine (Code Review) 06 May '24

06 May '24

Peter Marheine has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/82212?usp=email ) Change subject: dos/meson: add a hint for setting sys_root ...................................................................... dos/meson: add a hint for setting sys_root I found that cross-compiling with GCC 12.2.0 targeting DJGPP from Linux on x86_64 that meson used my system include directory (/usr/include/x86_64-linux-gnu/) and pulled in include files that are incompatible with DJGPP. Setting sys_root prevents meson from assuming they're compatible between the build and host systems, fixing those compile-time errors. TEST=meson setup --cross-file meson_cross/i586_djgpp_dos.txt; ninja libflashrom.h no longer causes "features.h: No such file or directory" errors via /usr/include/x86_64-linux-gnu/sys/types.h Change-Id: Ib9cf70f6f94782c5303fb232aaf4a46192907f66 Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> --- M meson_cross/i586_djgpp_dos.txt 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/82212/1 diff --git a/meson_cross/i586_djgpp_dos.txt b/meson_cross/i586_djgpp_dos.txt index 66d5ed0..3d97aab 100644 --- a/meson_cross/i586_djgpp_dos.txt +++ b/meson_cross/i586_djgpp_dos.txt @@ -5,6 +5,11 @@ # Make sure pkg-config can find your self compiles libpci # or add the path of your libpci.pc as 'pkg_config_libdir' # under [properies] below. +# +# If cross-compiling, you may need to set sys_root in the [properties] +# section because meson otherwise assumes the same sysroot as the +# system on which you're building and will get the wrong include files +# (from /usr/include/x86_64 for example) among other possible issues. [binaries] c = 'i586-pc-msdosdjgpp-gcc' @@ -27,3 +32,4 @@ ich_descriptors_tool = 'disabled' [properties] +sys_root = '/usr/local/djgpp' -- To view, visit https://review.coreboot.org/c/flashrom/+/82212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ib9cf70f6f94782c5303fb232aaf4a46192907f66 Gerrit-Change-Number: 82212 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: newchange

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[XS] Change in flashrom[main]: dos: mark myusec_delay static
by Peter Marheine (Code Review) 06 May '24

06 May '24

Peter Marheine has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/82213?usp=email ) Change subject: dos: mark myusec_delay static ...................................................................... dos: mark myusec_delay static If not static, this causes a compile-time error because it doesn't have a prototype. TEST=meson setup --cross-file meson_cross/i586_djgpp_dos.txt; ninja Change-Id: I1a43d89b9aabea7dab302350b1abf6bf613a3449 Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> --- M udelay_dos.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/13/82213/1 diff --git a/udelay_dos.c b/udelay_dos.c index 4a29f73..61493fc 100644 --- a/udelay_dos.c +++ b/udelay_dos.c @@ -28,7 +28,7 @@ /* loops per microsecond */ static unsigned long micro = 1; -__attribute__ ((noinline)) void myusec_delay(unsigned int usecs) +__attribute__ ((noinline)) static void myusec_delay(unsigned int usecs) { unsigned long i; for (i = 0; i < usecs * micro; i++) { -- To view, visit https://review.coreboot.org/c/flashrom/+/82213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I1a43d89b9aabea7dab302350b1abf6bf613a3449 Gerrit-Change-Number: 82213 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in flashrom[main]: Make sleep threshold for delays configurable
by Peter Marheine (Code Review) 06 May '24

06 May '24

Attention is currently required from: Peter Marheine, Thomas Heijligen. Hello Anastasia Klimchuk, Thomas Heijligen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/81606?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Make sleep threshold for delays configurable ...................................................................... Make sleep threshold for delays configurable This allows the minimum time that default_delay() will choose to sleep for instead of polling to be configured at build-time. The default remains unchanged at 100 milliseconds for now. The test's correctness has been checked by testing with minimum sleep time left at its default and set to a non-default value smaller than 100 microseconds (both pass without sleeping, verified with strace) and with the minimum sleep time set to 0 (causing the test to be skipped). The configured value from the macro needs to be stored in a const to avoid -Werror=type-limits errors when configured to be zero. Change-Id: Ida96e0816ac914ed69d6fd82ad90ebe89cdef1cc Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> --- M Makefile M meson.build M meson_options.txt M tests/udelay.c M udelay.c M udelay_dos.c 6 files changed, 38 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/06/81606/5 -- To view, visit https://review.coreboot.org/c/flashrom/+/81606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ida96e0816ac914ed69d6fd82ad90ebe89cdef1cc Gerrit-Change-Number: 81606 Gerrit-PatchSet: 5 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: newpatchset

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[XS] Change in flashrom[main]: flashrom: Change chip unlock error to warning
by Hsuan-ting Chen (Code Review) 06 May '24

06 May '24

Attention is currently required from: Brian Norris, Nikolai Artemiev. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/82175?usp=email ) Change subject: flashrom: Change chip unlock error to warning ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/82175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I14c3b55e387443909ca1efab2fc1901f87dd66d6 Gerrit-Change-Number: 82175 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Brian Norris <briannorris(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 06 May 2024 03:36:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in flashrom[main]: doc: Add user doc with links to ChromeOS documents
by Hsuan-ting Chen (Code Review) 06 May '24

06 May '24

Attention is currently required from: Anastasia Klimchuk, Stefan Reinauer, Thomas Heijligen. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/82181?usp=email ) Change subject: doc: Add user doc with links to ChromeOS documents ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > Hsuan-ting, apart from reviewing this patch, I wanted to ask maybe you would agree to maintain this […] Sounds good! -- To view, visit https://review.coreboot.org/c/flashrom/+/82181?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If7b06c077b34f73bc6c33f617332dfc32b982c12 Gerrit-Change-Number: 82181 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 06 May 2024 03:18:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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