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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58025?usp=email )
Change subject: flashchips: Add support for GigaDevice GD25LR256E, GD251R512ME
......................................................................
Patch Set 10:
(2 comments)
Patchset:
PS8:
> Many thanks to Victor on the mailing list for giving datasheets, I did a review and added some comme […]
Done
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/58025/comment/d548fbcd_930d8f84 :
PS8, Line 6552: .name = "GD25LR256E",
> This is out of order, both entries need to be moved after GD25LQ80 and just before GD25Q10
Done
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Attention is currently required from: Angel Pons, Martin L Roth, Martin Roth, Nikolai Artemiev, Peter Marheine, Raj Astekar, Ravishankar Sarawadi, Wonkyu Kim.
Anastasia Klimchuk has uploaded a new patch set (#10) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/flashrom/+/58025?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: flashchips: Add support for GigaDevice GD25LR256E, GD251R512ME
......................................................................
flashchips: Add support for GigaDevice GD25LR256E, GD251R512ME
BUG=none
BRANCH=none
TEST= Flash image using Flashrom Tool
flashrom -p raiden_debug_spi -w <test_binary>
flashrom -p dediprog -w <test_binary>
Also tested by two people on the mailing list:
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/TCT5…
Change-Id: I2fe6bc1219cd1ee19b93caabab69de938cfc44b0
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M flashchips.c
M include/flashchips.h
2 files changed, 112 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/58025/10
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Anastasia Klimchuk has uploaded a new patch set (#9) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/flashrom/+/58025?usp=email )
The following approvals got outdated and were removed:
Code-Review+1 by Peter Marheine
Change subject: flashchips: Add support for GigaDevice GD25LR256E, GD251R512ME
......................................................................
flashchips: Add support for GigaDevice GD25LR256E, GD251R512ME
BUG=none
BRANCH=none
TEST= Flash image using Flashrom Tool
flashrom -p raiden_debug_spi -w <test_binary>
flashrom -p dediprog -w <test_binary>
Also tested by two people on the mailing list:
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/TCT5…
Change-Id: I2fe6bc1219cd1ee19b93caabab69de938cfc44b0
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M flashchips.c
M include/flashchips.h
2 files changed, 112 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/58025/9
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Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/82393?usp=email )
Change subject: erasure_layout: Fix get_flash_region bug
......................................................................
Patch Set 8:
(1 comment)
File erasure_layout.c:
https://review.coreboot.org/c/flashrom/+/82393/comment/76e0ed80_c0befa3e :
PS5, Line 335: region_end - region_start
> If region end is inclusive, this needs to be +1 byte... am I right? (because the 3rd arg is length) […]
Yes. It took a little doing, but I added a test that fails unless this has `+ 1` on it.
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Hello Aarya, Alexander Goncharov, Anastasia Klimchuk, Nikolai Artemiev, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/82393?usp=email
to look at the new patch set (#9).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: erasure_layout: Fix get_flash_region bug
......................................................................
erasure_layout: Fix get_flash_region bug
When flash regions are protected, erase could incorrectly erase regions
which were meant to be protected by requesting the correct size but
using an erase opcode with coarser granularity than desired (for
instance using a 16-byte erase command while attempting to erase only 8
bytes).
This fixes that by exchanging the nesting of the loops over erase blocks
and flash regions.
Old:
- Select erasefns
- Loop over blocks to erase for each selected erasefn
- Loop over programmer flash regions within erase block
- Erase regions (may fail since selected erasefn will be
too big if flash region is smaller than erase block)
New:
- Loop over programmer flash regions within erase block
- Select erasefns within programer flash region
- Loop over blocks to erase for each selected erasefn
- Erase regions
Eraser selection and erasing has also been factored out into a helper
function to manage nesting depth.
TEST=New test cases pass, whereas some of them fail without the changes
to erasure_layout.c
BUG=https://ticket.coreboot.org/issues/525
Change-Id: Ic5bf9d0f0e4a94c48d6f6e74e3cb9cccdc7adec9
Co-authored-by: Nikolai Artemiev <nartemiev(a)google.com>
Co-authored-by: Anastasia Klimchuk <aklm(a)flashrom.org>
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Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
Signed-off-by: Peter Marheine <pmarheine(a)chromium.org>
---
M erasure_layout.c
M tests/erase_func_algo.c
M tests/tests.c
M tests/tests.h
4 files changed, 489 insertions(+), 96 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/82393/9
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Hello Aarya, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/82496?usp=email
to look at the new patch set (#2).
Change subject: Correct get_flash_region() to use inclusive upper bounds
......................................................................
Correct get_flash_region() to use inclusive upper bounds
get_flash_region() emits a struct flash_region, which uses chipoff_t for
the start and end addresses of a region. chipoff_t is defined as a valid
flash address, so it was wrong to be setting the end address to start +
len; this is clearly wrong in the case where there is a single region
because setting end to the flash size generates an address that is
beyond the end of the chip (due to zero-indexing).
This changes the one actual implementation of .get_region in ichspi.c to
use inclusive upper bounds, and corrects all callers of
get_flash_region() to treat the upper bounds as inclusive. Overall this
reduces complexity slightly by removing more downward adjustments by 1
than it needs to add upward adjustments.
Change-Id: Ia0ca867aef33b598c2697fc264807fa5e29683ec
Signed-off-by: Peter Marheine <pmarheine(a)chromium.org>
---
M erasure_layout.c
M flashrom.c
M ichspi.c
3 files changed, 20 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/82496/2
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Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/82393?usp=email )
Change subject: erasure_layout: Fix get_flash_region bug
......................................................................
Patch Set 7:
(1 comment)
File erasure_layout.c:
https://review.coreboot.org/c/flashrom/+/82393/comment/67e993db_d6350f75 :
PS5, Line 369: len = min(region_end, region.end - 1) - addr + 1;
> I actually think `ich_get_region` (the only existing implementation of `get_region`) is wrong here, […]
I added a new parent change that fixes get_flash_region's incorrect use of chipoff_t (now the upper bound is actually inclusive), so there's no more inconsistency here.
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