May 2024 - flashrom-gerrit - mail.coreboot.org

[S] Change in flashrom[main]: flashchips: Add support for Boya B25Q64AS
by Malcolm Boyes (Code Review) 19 May '24

19 May '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer. Malcolm Boyes has posted comments on this change by Malcolm Boyes. ( https://review.coreboot.org/c/flashrom/+/82259?usp=email ) Change subject: flashchips: Add support for Boya B25Q64AS ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/82259/comment/127332cb_e667dede?us… : PS2, Line 14: boyesm > Sorry I missed this: I think it's more standard to put your name here (Malcolm Boyes). […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/82259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I05ecf2b118902db974544d86e023a348912371dd Gerrit-Change-Number: 82259 Gerrit-PatchSet: 3 Gerrit-Owner: Malcolm Boyes <boyesmalcolm(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Sun, 19 May 2024 15:24:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: flashchips: Add support for Boya B25Q64AS
by Malcolm Boyes (Code Review) 19 May '24

19 May '24

Attention is currently required from: Malcolm Boyes, Nikolai Artemiev, Stefan Reinauer. Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/82259?usp=email to look at the new patch set (#3). Change subject: flashchips: Add support for Boya B25Q64AS ...................................................................... flashchips: Add support for Boya B25Q64AS The B25Q64AS has been tested by ch341a programmer: read, write, erase Datasheet: https://archive.org/details/1912111437-boyamicro-by-25-q-64-assig-c-383793 Change-Id: I05ecf2b118902db974544d86e023a348912371dd Signed-off-by: Malcolm Boyes <boyesmalcolm(a)gmail.com> --- M flashchips.c M include/flashchips.h 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/59/82259/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/82259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I05ecf2b118902db974544d86e023a348912371dd Gerrit-Change-Number: 82259 Gerrit-PatchSet: 3 Gerrit-Owner: Malcolm Boyes <boyesmalcolm(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Malcolm Boyes <boyesmalcolm(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com>

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[M] Change in flashrom[main]: ichspi.c: Add support for region 9 and beyond in Meteor Lake
by Anastasia Klimchuk (Code Review) 19 May '24

19 May '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/81357?usp=email ) Change subject: ichspi.c: Add support for region 9 and beyond in Meteor Lake ...................................................................... ichspi.c: Add support for region 9 and beyond in Meteor Lake Since Meteor Lake, configuring region access for FREG9 and higher is necessary. This configuration is determined using BIOS_BM registers: BIOS_BM_RAP (Offset 0x118): BIOS Master Read Access Permissions. Each bit [15:0] corresponds to a region [15:0]. A set bit grants BIOS master read access. BIOS_BM_WAP (Offset 0x11c): BIOS Master Write Access Permissions. Each bit [15:0] corresponds to a region [15:0]. A set bit grants BIOS master write/erase access. Move CHIPSET_METEOR_LAKE to the bottom of the ich_chipset list to ensure that all the newer chipsets in the future will use BIOS_BM check by default. BUG=b:319773700, b:304439294 BUG=b:319336080 TEST=On MTL, use flashrom -VV to see correct FREG9 access TEST=On ADL, use flashrom -VV to see not break anything TEST=On APL, use flashrom -VV to see not break anything Change-Id: I1e06e7b3d470423a6014e623826d9234fdebfbf9 Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/81357 Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M ichspi.c M include/programmer.h 2 files changed, 67 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Jamie Ryu: Looks good to me, but someone else must approve Nikolai Artemiev: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/ichspi.c b/ichspi.c index bee5ec9..bef43b9 100644 --- a/ichspi.c +++ b/ichspi.c @@ -153,6 +153,9 @@ #define ICH9_FADDR_FLA 0x01ffffff #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ +#define ICH_REG_BIOS_BM_RAP 0x118 /* 16 Bits BIOS Master Read Access Permissions */ +#define ICH_REG_BIOS_BM_WAP 0x11c /* 16 Bits BIOS Master Write Access Permissions */ + #define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */ #define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */ @@ -1834,8 +1837,52 @@ "read-write", "write-only", "read-only", "locked" }; -static enum ich_access_protection ich9_handle_frap(struct fd_region *fd_regions, - uint32_t frap, unsigned int i) +static void ich_get_bios_region_access(uint16_t *region_read_access, + uint16_t *region_write_access) +{ + uint32_t tmp; + *region_read_access = 0; + *region_write_access = 0; + + if (ich_generation >= CHIPSET_METEOR_LAKE) { + /* + * Starting from Meteor Lake, we need to fetch the region + * read/write access permissions from the BIOS_BM registers + * because we need to support FREG9 or above. + */ + *region_read_access = mmio_readw(ich_spibar + ICH_REG_BIOS_BM_RAP); + *region_write_access = mmio_readw(ich_spibar + ICH_REG_BIOS_BM_WAP); + msg_pdbg("0x118: 0x%04"PRIx16" (BIOS_BM_RAP)\n", *region_read_access); + msg_pdbg("0x11a: 0x%04"PRIx16" (BIOS_BM_WAP)\n", *region_write_access); + } else { + /* + * FRAP - Flash Regions Access Permissions Register + * Bit Descriptions: + * 31:24 BIOS Master Write Access Grant (BMWAG) + * 23:16 BIOS Master Read Access Grant (BMRAG) + * 15:8 BIOS Region Write Access (BRWA) + * 7:0 BIOS Region Read Access (BRRA) + */ + tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); + msg_pdbg("0x50: 0x%08"PRIx32" (FRAP)\n", tmp); + msg_pdbg("BMWAG 0x%02"PRIx32", ", ICH_BMWAG(tmp)); + msg_pdbg("BMRAG 0x%02"PRIx32", ", ICH_BMRAG(tmp)); + msg_pdbg("BRWA 0x%02"PRIx32", ", ICH_BRWA(tmp)); + msg_pdbg("BRRA 0x%02"PRIx32"\n", ICH_BRRA(tmp)); + + *region_read_access = (uint16_t)ICH_BRRA(tmp); + *region_write_access = (uint16_t)ICH_BRWA(tmp); + } +} + +static unsigned int ich_get_defined_region_count(void) { + return (ich_generation >= CHIPSET_METEOR_LAKE) ? 16 : 8; +} + +static enum ich_access_protection ich9_handle_region_access(struct fd_region *fd_regions, + uint16_t region_read_access, + uint16_t region_write_access, + unsigned int i) { static const char *const region_names[] = { "Flash Descriptor", "BIOS", "Management Engine", @@ -1863,12 +1910,12 @@ } msg_pdbg("0x%02X: 0x%08"PRIx32" ", offset, freg); - if (i < 8) { - rwperms_idx = (((ICH_BRWA(frap) >> i) & 1) << 1) | - (((ICH_BRRA(frap) >> i) & 1) << 0); + if (i < ich_get_defined_region_count()) { + rwperms_idx = (((region_write_access >> i) & 1) << 1) | + (((region_read_access >> i) & 1) << 0); rwperms = access_perms_to_protection[rwperms_idx]; } else { - /* Datasheets don't define any access bits for regions > 7. We + /* Datasheets might not define all the access bits for regions. We can't rely on the actual descriptor settings either as there are several overrides for them (those by other masters are not even readable by us, *shrug*). */ @@ -2059,11 +2106,11 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: - case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: + case CHIPSET_METEOR_LAKE: *num_pr = 6; /* Includes GPR0 */ *reg_pr0 = PCH100_REG_FPR0; swseq->reg_ssfsc = PCH100_REG_SSFSC; @@ -2099,11 +2146,11 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: - case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: + case CHIPSET_METEOR_LAKE: *num_freg = 16; break; default: @@ -2161,11 +2208,11 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: - case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: + case CHIPSET_METEOR_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08"PRIx32" (DLOCK)\n", tmp); prettyprint_pch100_reg_dlock(tmp); @@ -2175,16 +2222,15 @@ } if (desc_valid) { - tmp = mmio_readl(spibar + ICH9_REG_FRAP); - msg_pdbg("0x50: 0x%08"PRIx32" (FRAP)\n", tmp); - msg_pdbg("BMWAG 0x%02"PRIx32", ", ICH_BMWAG(tmp)); - msg_pdbg("BMRAG 0x%02"PRIx32", ", ICH_BMRAG(tmp)); - msg_pdbg("BRWA 0x%02"PRIx32", ", ICH_BRWA(tmp)); - msg_pdbg("BRRA 0x%02"PRIx32"\n", ICH_BRRA(tmp)); + /* Get the region access data from FRAP/BIOS_BM */ + uint16_t region_read_access, region_write_access; + ich_get_bios_region_access(&region_read_access, &region_write_access); - /* Handle FREGx and FRAP registers */ + /* Handle FREGx and region access registers */ for (i = 0; i < num_freg; i++) - ich_spi_rw_restricted |= ich9_handle_frap(hwseq_data.fd_regions, tmp, i); + ich_spi_rw_restricted |= ich9_handle_region_access(hwseq_data.fd_regions, + region_read_access, + region_write_access, i); if (ich_spi_rw_restricted) msg_pinfo("Not all flash regions are freely accessible by flashrom. This is " "most likely\ndue to an active ME. Please see " @@ -2242,12 +2288,12 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: - case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: case CHIPSET_BAYTRAIL: case CHIPSET_ELKHART_LAKE: + case CHIPSET_METEOR_LAKE: break; default: ichspi_bbar = mmio_readl(spibar + ICH9_REG_BBAR); @@ -2282,11 +2328,11 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: - case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: + case CHIPSET_METEOR_LAKE: break; default: tmp = mmio_readl(spibar + ICH9_REG_FPB); diff --git a/include/programmer.h b/include/programmer.h index 939c8de..8ef6ffd 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -357,11 +357,12 @@ CHIPSET_400_SERIES_COMET_POINT, CHIPSET_500_SERIES_TIGER_POINT, CHIPSET_600_SERIES_ALDER_POINT, - CHIPSET_METEOR_LAKE, CHIPSET_APOLLO_LAKE, CHIPSET_GEMINI_LAKE, CHIPSET_JASPER_LAKE, CHIPSET_ELKHART_LAKE, + /* All chipsets after METEOR_LAKE should support checking BIOS_BM to get read/write access to of FREG0~15 */ + CHIPSET_METEOR_LAKE, }; /* ichspi.c */ -- To view, visit https://review.coreboot.org/c/flashrom/+/81357?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I1e06e7b3d470423a6014e623826d9234fdebfbf9 Gerrit-Change-Number: 81357 Gerrit-PatchSet: 13 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>

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[XS] Change in flashrom[main]: flashchips.c: mark XM25QU256C as tested for probe/read/erase/write.
by Anastasia Klimchuk (Code Review) 19 May '24

19 May '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/82459?usp=email ) Change subject: flashchips.c: mark XM25QU256C as tested for probe/read/erase/write. ...................................................................... flashchips.c: mark XM25QU256C as tested for probe/read/erase/write. Mark XM25QU256C as tested for probe/read/erase/write. Found in a Clevo V560TU, tested with a CH341a programmer. Flashrom log: https://paste.flashrom.org/view.php?id=3732 Change-Id: Ia9226b71e355d2cc736af0ac4e039e8a3b73a84b Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82459 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Anastasia Klimchuk: Looks good to me, approved build bot (Jenkins): Verified diff --git a/flashchips.c b/flashchips.c index 1917ed6..59edeb3 100644 --- a/flashchips.c +++ b/flashchips.c @@ -21876,7 +21876,7 @@ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_4BA_WRITE, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = -- To view, visit https://review.coreboot.org/c/flashrom/+/82459?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ia9226b71e355d2cc736af0ac4e039e8a3b73a84b Gerrit-Change-Number: 82459 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: ch347_spi: Add driver support for CH347F packaging
by Nicholas Chin (Code Review) 19 May '24

19 May '24

Attention is currently required from: Paul Menzel, ZhiYuanNJ. Nicholas Chin has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82193?usp=email ) Change subject: ch347_spi: Add driver support for CH347F packaging ...................................................................... Patch Set 9: Code-Review+1 (2 comments) File ch347_spi.c: https://review.coreboot.org/c/flashrom/+/82193/comment/806a0357_db1e68fa?us… : PS9, Line 10: Remove extra spaces https://review.coreboot.org/c/flashrom/+/82193/comment/3267930a_e5a3f4c4?us… : PS9, Line 307: Remove trailing space -- To view, visit https://review.coreboot.org/c/flashrom/+/82193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Gerrit-Change-Number: 82193 Gerrit-PatchSet: 9 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: ZhiYuanNJ Gerrit-Comment-Date: Sun, 19 May 2024 02:01:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in flashrom[main]: doc: Add doc for dummyflasher
by Sergii Dmytruk (Code Review) 18 May '24

18 May '24

Attention is currently required from: Anastasia Klimchuk, Thomas Heijligen. Sergii Dmytruk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/82482?usp=email ) Change subject: doc: Add doc for dummyflasher ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/82482?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I1e2039a3dcb958e96c4f1ff7b99a5629c3e83ed1 Gerrit-Change-Number: 82482 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Sat, 18 May 2024 20:50:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in flashrom[main]: doc: Add doc for dummyflasher
by Anastasia Klimchuk (Code Review) 17 May '24

17 May '24

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/82482?usp=email ) Change subject: doc: Add doc for dummyflasher ...................................................................... doc: Add doc for dummyflasher Change-Id: I1e2039a3dcb958e96c4f1ff7b99a5629c3e83ed1 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- A doc/supported_hw/supported_prog/dummyflasher.rst M doc/supported_hw/supported_prog/index.rst 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/82/82482/1 diff --git a/doc/supported_hw/supported_prog/dummyflasher.rst b/doc/supported_hw/supported_prog/dummyflasher.rst new file mode 100644 index 0000000..d11f59c --- /dev/null +++ b/doc/supported_hw/supported_prog/dummyflasher.rst @@ -0,0 +1,14 @@ +============ +Dummyflasher +============ + +Dummyflasher programmer is software-only implementation of a flashrom programmer. In other words, +it is an emulator which operates on in-memory arrays of bytes instead of a real chip. Dummyflasher does not interact with any hardware. + +This programmer is actively used in unit tests. + +Also, since dummyflasher implements all of the programmers APIs, it can be used as an example or as a starting point for implementing a new programmer. + +Related documents: + +* :doc:`/contrib_howtos/how_to_add_unit_test` diff --git a/doc/supported_hw/supported_prog/index.rst b/doc/supported_hw/supported_prog/index.rst index d8131a6..3f05c25 100644 --- a/doc/supported_hw/supported_prog/index.rst +++ b/doc/supported_hw/supported_prog/index.rst @@ -13,4 +13,5 @@ .. toctree:: :maxdepth: 1 + dummyflasher serprog/index -- To view, visit https://review.coreboot.org/c/flashrom/+/82482?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I1e2039a3dcb958e96c4f1ff7b99a5629c3e83ed1 Gerrit-Change-Number: 82482 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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[M] Change in flashrom[main]: flashchips: Add support for chip model GD25LF128E
by Anastasia Klimchuk (Code Review) 17 May '24

17 May '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/82332?usp=email ) Change subject: flashchips: Add support for chip model GD25LF128E ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/82332/comment/3cc45823_5d7eb072 : PS1, Line 7: Add (or update) chip models <list models> > For this commit you can be more specific, because you know what model you adding. […] Done File flashchips.c: https://review.coreboot.org/c/flashrom/+/82332/comment/b31f8253_04492922 : PS1, Line 6506: .model_id = GIGADEVICE_GD25LF128E, > This macro should be added in the same patch as chip definition. […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/82332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I71fdc7ea1aea69d14db6af3bac2da3e7bee8abbe Gerrit-Change-Number: 82332 Gerrit-PatchSet: 2 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 17 May 2024 12:11:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in flashrom[main]: flashchips: Add support for chip model GD25LF128E
by Anastasia Klimchuk (Code Review) 17 May '24

17 May '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has uploaded a new patch set (#2) to the change originally created by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/82332?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: flashchips: Add support for chip model GD25LF128E ...................................................................... flashchips: Add support for chip model GD25LF128E Adding GD25LF128E to flashchip.c GD25LF128E: 1.8V 128Mbit, QE default fixed at 1. Datasheet link https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-0… Change-Id: I71fdc7ea1aea69d14db6af3bac2da3e7bee8abbe Signed-off-by: Victor Lim <vlim(a)gigadevice.com> Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M flashchips.c M include/flashchips.h 2 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/82332/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/82332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I71fdc7ea1aea69d14db6af3bac2da3e7bee8abbe Gerrit-Change-Number: 82332 Gerrit-PatchSet: 2 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[main]: flashchips: Add support for GigaDevice GD25LR256E, GD251R512ME
by Anastasia Klimchuk (Code Review) 17 May '24

17 May '24

Attention is currently required from: Angel Pons, Martin L Roth, Martin Roth, Nikolai Artemiev, Peter Marheine, Raj Astekar, Ravishankar Sarawadi, Wonkyu Kim. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58025?usp=email ) Change subject: flashchips: Add support for GigaDevice GD25LR256E, GD251R512ME ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: I did a review, rebased the patch on head and fixed all of my own comments :) Now I need someone else to review/approve. Nikolai, Peter, would you review this? Especially whether my comment is correct, that BP4 in datasheets works as TB. Datasheets are attached to the thread on the mailing list "Support for GD25LR512ME flash chip" Thank you! -- To view, visit https://review.coreboot.org/c/flashrom/+/58025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I2fe6bc1219cd1ee19b93caabab69de938cfc44b0 Gerrit-Change-Number: 58025 Gerrit-PatchSet: 10 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Fri, 17 May 2024 09:29:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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