October 2024 - flashrom-gerrit

[L] Change in flashrom[main]: rpmc: add rpmc commands feature
by Peter Marheine (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Anastasia Klimchuk, Matti Finder. Peter Marheine has posted comments on this change by Matti Finder. ( https://review.coreboot.org/c/flashrom/+/84934?usp=email ) Change subject: rpmc: add rpmc commands feature ...................................................................... Patch Set 2: (1 comment) File include/rpmc.h: https://review.coreboot.org/c/flashrom/+/84934/comment/5b67ddf3_b8ad00be?us… : PS1, Line 37: uint8_t status; > Within JESD260 there is a specific 8-bit extended status register defined. […] I don't mind returning 0x80 on success, but the documentation comments should be clear on how to interpret the return value. -- To view, visit https://review.coreboot.org/c/flashrom/+/84934?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6ab3d0446e9fd674b20550fdbfaf499b8d4a9b38 Gerrit-Change-Number: 84934 Gerrit-PatchSet: 2 Gerrit-Owner: Matti Finder <matti.finder(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Matti Finder <matti.finder(a)gmail.com> Gerrit-Comment-Date: Thu, 31 Oct 2024 22:36:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matti Finder <matti.finder(a)gmail.com> Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org>

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[L] Change in flashrom[main]: rpmc: add rpmc commands feature
by Matti Finder (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Anastasia Klimchuk, Peter Marheine. Matti Finder has posted comments on this change by Matti Finder. ( https://review.coreboot.org/c/flashrom/+/84934?usp=email ) Change subject: rpmc: add rpmc commands feature ...................................................................... Patch Set 2: (3 comments) File include/rpmc.h: https://review.coreboot.org/c/flashrom/+/84934/comment/d7912236_6d9d1418?us… : PS1, Line 37: uint8_t status; > It looks like you use status values in the CLI and 0x80 always indicates success, but that's not a v […] Within JESD260 there is a specific 8-bit extended status register defined. The status for last command success is 0b10000000, hence the 0x80. The status 0 is only used as the state immideatly after reboot, so it should never happen after one of our transmissions. So we could also use it as a return value without losing valuable data. What would you prefer keeping it close to JESD260 and returning the status register value, and documenting it better (maybe adding a enum for the values). Or cheating a bit and returning 0 on success instead of 0x80. I currently prefer the second option, with some additional defines for the bits. File meson.build: https://review.coreboot.org/c/flashrom/+/84934/comment/aa3c01a9_54dc9fd4?us… : PS1, Line 177: enabled > `enabled` is only true if the feature is set to `enabled` (not `auto`). […] Done File rpmc.c: https://review.coreboot.org/c/flashrom/+/84934/comment/794bd7c8_11441024?us… : PS1, Line 287: unsigned char msg[RPMC_UPDATE_HMAC_KEY_MSG_LENGTH]; > I'd prefer to use initializers for arrays like this (throughout this file), to make it less prone to […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/84934?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6ab3d0446e9fd674b20550fdbfaf499b8d4a9b38 Gerrit-Change-Number: 84934 Gerrit-PatchSet: 2 Gerrit-Owner: Matti Finder <matti.finder(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Thu, 31 Oct 2024 16:21:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org>

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[L] Change in flashrom[main]: rpmc: add rpmc commands feature
by Matti Finder (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Anastasia Klimchuk, Matti Finder. Hello Anastasia Klimchuk, Peter Marheine, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/84934?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: rpmc: add rpmc commands feature ...................................................................... rpmc: add rpmc commands feature Added optional support for all the commands specified in JESD260. Added a new optional dependency to openssls libcrypto. Added parsing for the rpmc parameter sfdp table. Added necessary rpmc parameter information to flashchips struct and the flash hardening feature to enable rpmc commands. Enables future use of these commands in the cli_client and also libflashrom. Change-Id: I6ab3d0446e9fd674b20550fdbfaf499b8d4a9b38 Signed-off-by: Matti Finder <matti.finder(a)gmail.com> --- M include/flash.h A include/rpmc.h M meson.build M meson_options.txt A rpmc.c M sfdp.c 6 files changed, 670 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/84934/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/84934?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6ab3d0446e9fd674b20550fdbfaf499b8d4a9b38 Gerrit-Change-Number: 84934 Gerrit-PatchSet: 2 Gerrit-Owner: Matti Finder <matti.finder(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Matti Finder <matti.finder(a)gmail.com>

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[M] Change in flashrom[main]: Display progress for what is actually erased/written
by Sergii Dmytruk (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Anastasia Klimchuk. Sergii Dmytruk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/84439?usp=email ) Change subject: Display progress for what is actually erased/written ...................................................................... Patch Set 17: Code-Review+2 (2 comments) Patchset: PS16: > Just out of curiosity I ran the test case from here https://review.coreboot. […] Read also reaches 50% for the second command: ``` Found Winbond flash chip "W25Q128.V" (16384 kB, SPI) on dummy. Reading old flash chip contents... [READ: 100%]...done. Updating flash chip contents... [READ: 50%][ERASE: 50%][WRITE: 100%]...Erase/write done from 0 to ffffff Verifying flash... [READ: 100%]...VERIFIED. ``` Erasure is probably the result of selecting more fine-grained erasure functions in `erasure_layout.c`. Not sure about reads. File flashrom.c: https://review.coreboot.org/c/flashrom/+/84439/comment/a8f29ee5_d947e26b?us… : PS13, Line 1270: // FIXME: round up to granularity? > Okay so I will close this (and the other one). […] Sure. -- To view, visit https://review.coreboot.org/c/flashrom/+/84439?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I88ac4d40f1b6ccc1636b1efb690d8d68bdebec08 Gerrit-Change-Number: 84439 Gerrit-PatchSet: 17 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 31 Oct 2024 14:44:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>

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[S] Change in flashrom[main]: flashchips: add GD25F128F
by Anastasia Klimchuk (Code Review) 31 Oct '24

31 Oct '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/84827?usp=email ) Change subject: flashchips: add GD25F128F ...................................................................... flashchips: add GD25F128F GD25F128F: 3V 128Mbit, high performance Tested on ch347 with erase, write, read, and protection Corrected the OTP statement. Change-Id: I14c0905f50e92492287d50f8377790b997c4acfe Signed-off-by: Victor <vlim(a)gigadevice.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84827 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c M include/flashchips.h 2 files changed, 46 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index f480078..c32159d 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8188,6 +8188,51 @@ .decode_range = DECODE_RANGE_SPI25, }, +{ + .vendor = "GigaDevice", + .name = "GD25F128F", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25F128F, + .total_size = 16384, + .page_size = 256, + /* OTP: 3x2048B; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2 | FEATURE_WRSR3, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */ + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + .reg_bits = + { + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */ + }, + .decode_range = DECODE_RANGE_SPI25, + }, + { .vendor = "GigaDevice", .name = "GD25F256F", diff --git a/include/flashchips.h b/include/flashchips.h index 886ddc9..719486e 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -402,6 +402,7 @@ #define GIGADEVICE_GD25VQ80C 0x4214 #define GIGADEVICE_GD25VQ16C 0x4215 #define GIGADEVICE_GD25F64F 0x4317 +#define GIGADEVICE_GD25F128F 0x4318 #define GIGADEVICE_GD25F256F 0x4319 #define GIGADEVICE_GD25LQ40 0x6013 #define GIGADEVICE_GD25LQ80 0x6014 -- To view, visit https://review.coreboot.org/c/flashrom/+/84827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I14c0905f50e92492287d50f8377790b997c4acfe Gerrit-Change-Number: 84827 Gerrit-PatchSet: 3 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: doc: Add chip models support into recent development
by Anastasia Klimchuk (Code Review) 30 Oct '24

30 Oct '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/84870?usp=email ) Change subject: doc: Add chip models support into recent development ...................................................................... doc: Add chip models support into recent development Change-Id: I9b96902a02b83d35f0a0f221bd1678b7edf99dad Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84870 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Peter Marheine <pmarheine(a)chromium.org> --- M doc/release_notes/devel.rst 1 file changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Peter Marheine: Looks good to me, approved diff --git a/doc/release_notes/devel.rst b/doc/release_notes/devel.rst index c542bea..f54b5f1 100644 --- a/doc/release_notes/devel.rst +++ b/doc/release_notes/devel.rst @@ -26,6 +26,7 @@ New Feature =========== + Libpci 3.13.0 and onwards support ECAM to access pci registers. Flashrom will be moved to ECAM from IO port 0xcf8/0xcfc if the libpci version is >= 3.13.0. The ECAM has been supported for a very long time, most platforms should support @@ -39,4 +40,48 @@ Chipset support =============== + Added Raptor Point PCH support. + +Chip model support added +======================== + +* FM25Q04 +* FM25Q64 +* FM25Q128 + +* GD25B128E +* GD25B256E +* GD25B512MF +* GD25F64F +* GD25F256F +* GD25R128E +* GD25R256E +* GD25R512MF +* GD25LB256F +* GD25LB512ME +* GD25LB512MF +* GD25LR256F +* GD25LR512MF +* GD25LF256F +* GD25LF512MF + +* MX25U25645G +* MX77U51250F + +* W25Q32JV_M + +* XM25LU64C +* XM25QH32C +* XM25QH32D +* XM25QH64D +* XM25QH128D +* XM25QH256D +* XM25QH512C +* XM25QH512D +* XM25QU16C +* XM25QU32C +* XM25QU128D +* XM25QU256D +* XM25QU512C +* XM25QU512D -- To view, visit https://review.coreboot.org/c/flashrom/+/84870?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9b96902a02b83d35f0a0f221bd1678b7edf99dad Gerrit-Change-Number: 84870 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in flashrom[main]: rpmc: add rpmc commands feature
by Peter Marheine (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Anastasia Klimchuk, Matti Finder. Peter Marheine has posted comments on this change by Matti Finder. ( https://review.coreboot.org/c/flashrom/+/84934?usp=email ) Change subject: rpmc: add rpmc commands feature ...................................................................... Patch Set 1: (1 comment) File include/rpmc.h: https://review.coreboot.org/c/flashrom/+/84934/comment/38966ef0_ec9b0810?us… : PS1, Line 37: uint8_t status; It looks like you use status values in the CLI and 0x80 always indicates success, but that's not a value I would expect to indicate success. Can you add a little documentation here and perhaps also explain better what the function return values mean (even if it's just referring to an explanation attached to this field)? -- To view, visit https://review.coreboot.org/c/flashrom/+/84934?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6ab3d0446e9fd674b20550fdbfaf499b8d4a9b38 Gerrit-Change-Number: 84934 Gerrit-PatchSet: 1 Gerrit-Owner: Matti Finder <matti.finder(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Matti Finder <matti.finder(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Oct 2024 22:35:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in flashrom[main]: rpmc: add rpmc commands feature
by Peter Marheine (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Anastasia Klimchuk, Matti Finder. Peter Marheine has posted comments on this change by Matti Finder. ( https://review.coreboot.org/c/flashrom/+/84934?usp=email ) Change subject: rpmc: add rpmc commands feature ...................................................................... Patch Set 1: (2 comments) File meson.build: https://review.coreboot.org/c/flashrom/+/84934/comment/6fb0d9a0_4affdf5c?us… : PS1, Line 177: enabled `enabled` is only true if the feature is set to `enabled` (not `auto`). You probably want `get_option('rpmc').allowed()` since that's true if it's either `auto` or `enabled`. File rpmc.c: https://review.coreboot.org/c/flashrom/+/84934/comment/7534816b_ddc98ec5?us… : PS1, Line 287: unsigned char msg[RPMC_UPDATE_HMAC_KEY_MSG_LENGTH]; I'd prefer to use initializers for arrays like this (throughout this file), to make it less prone to length-related errors. ``` unsigned char msg[RPMC_UPDATE_HMAC_KEY_MSG_LENGTH] = { flash->chip->rpmc_ctx.op1_opcode, 0x01, counter_address, ... }; ``` -- To view, visit https://review.coreboot.org/c/flashrom/+/84934?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6ab3d0446e9fd674b20550fdbfaf499b8d4a9b38 Gerrit-Change-Number: 84934 Gerrit-PatchSet: 1 Gerrit-Owner: Matti Finder <matti.finder(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Matti Finder <matti.finder(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Oct 2024 22:30:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in flashrom[main]: cli_client: Add rpmc command support
by Matti Finder (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Anastasia Klimchuk, Peter Marheine. Matti Finder has posted comments on this change by Matti Finder. ( https://review.coreboot.org/c/flashrom/+/84840?usp=email ) Change subject: cli_client: Add rpmc command support ...................................................................... Patch Set 5: (8 comments) This change is ready for review. Patchset: PS4: > Oh one more thing I forgot to mention sorry... […] 1) I think that makes sense I have created a new change at ID 84934 for the first commit and left this one as the documenation and cli_client change. 2) Done. 3) Yes I would like to become a maintainer for the rpmc feature :) Commit Message: https://review.coreboot.org/c/flashrom/+/84840/comment/f74ea504_d66478d3?us… : PS4, Line 21: usefull > usefull -> useful (typo) […] Done File cli_classic.c: https://review.coreboot.org/c/flashrom/+/84840/comment/4753fab4_29821d26?us… : PS4, Line 147: #if CONFIG_RPMC_ENABLED == 1 : "RPMC COMMANDS\n" : " --get-rpmc-status read the extended status\n" : " --write-root-key write the root key register\n" : " --update-hmac-key update the hmac key register\n" : " --increment-counter <previous>\n" : " increment rpmc counter\n" : " --get-counter get rpmc counter\n" : "RPMC OPTIONS\n" : " --counter-address <number> counter address (default: 0)\n" : " --rpmc-root-key <keyfile> rpmc root key file\n" : " --key-data <keydata> hex number to use as key data (default: 0)\n" : #endif // CONFIG_RPMC_ENABLED > These new commands need to also be documented on the manpage. […] Done https://review.coreboot.org/c/flashrom/+/84840/comment/8fc2ba09_c9679c38?us… : PS4, Line 1323: if (options.rpmc_read_data) : ret = rpmc_read_data(fill_flash); > I think having code in a separate file rpmc.c is better, you don't need to move it. Keep rpmc. […] Ok then File include/flash.h: https://review.coreboot.org/c/flashrom/+/84840/comment/7edbebcc_d5824ca9?us… : PS4, Line 553: implement > I know it's a small thing, but if you start with uppercase it would look better. This comment doesn't really make sense in the final commit, since it was more of an todo for me. I have removed it. https://review.coreboot.org/c/flashrom/+/84840/comment/fcf66055_c25ccc4d?us… : PS4, Line 575: /* : * all times in microsecond (us) : */ > Also small comment, but this can be 1-line comment, and starting with uppercase […] Done https://review.coreboot.org/c/flashrom/+/84840/comment/68c5445c_2d8c4f65?us… : PS4, Line 581: rpmc_ctx > I understand this goes into a flashchip definition? and you mentioned you tested on one chip? It wou […] This is sadly not as easily possible, since the chip reports itself with the same id as the W25Q128.V. So adding this feature would require changing the polling function to basically just be the same as the one for sfdp-capable chips. File meson.build: https://review.coreboot.org/c/flashrom/+/84840/comment/a486222c_9d85dce1?us… : PS4, Line 177: if libcrypto.found() : add_project_arguments('-DCONFIG_RPMC_ENABLED=1', language : 'c') > This ignores the meson option you added. […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/84840?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I36c823bbee65f256eb6edabe6f058321c9a0cfa1 Gerrit-Change-Number: 84840 Gerrit-PatchSet: 5 Gerrit-Owner: Matti Finder <matti.finder(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Wed, 30 Oct 2024 17:18:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org> Comment-In-Reply-To: Matti Finder <matti.finder(a)gmail.com>

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[L] Change in flashrom[main]: rpmc: add rpmc commands feature
by Matti Finder (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Peter Marheine. Matti Finder has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/84934?usp=email ) Change subject: rpmc: add rpmc commands feature ...................................................................... rpmc: add rpmc commands feature Added optional support for all the commands specified in JESD260. Added a new optional dependency to openssls libcrypto. Added parsing for the rpmc parameter sfdp table. Added necessary rpmc parameter information to flashchips struct and the flash hardening feature to enable rpmc commands. Enables future use of these commands in the cli_client and also libflashrom. Change-Id: I6ab3d0446e9fd674b20550fdbfaf499b8d4a9b38 Signed-off-by: Matti Finder <matti.finder(a)gmail.com> --- M include/flash.h A include/rpmc.h M meson.build M meson_options.txt A rpmc.c M sfdp.c 6 files changed, 666 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/84934/1 diff --git a/include/flash.h b/include/flash.h index d0e55af..ccac994 100644 --- a/include/flash.h +++ b/include/flash.h @@ -172,6 +172,11 @@ /* Whether chip has configuration register (RDCR/WRSR_EXT2 commands) */ #define FEATURE_CFGR (1 << 25) +/* + * Whether the chip supports serial flash hardening specified in JESD260 + */ +#define FEATURE_FLASH_HARDENING (1 << 26) + #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) #define UNERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0xff : 0x00) @@ -543,6 +548,32 @@ * and determines what protection range they select. */ enum decode_range_func decode_range; + + struct rpmc_config { + uint8_t op1_opcode; + uint8_t op2_opcode; + + unsigned int num_counters; + + /* + * Busy Polling Method : + * ‘0’: Poll for OP1 busy using OP2 Extended Status[0]. + * No OP1 Suspended State Support. + * ‘1’: Poll for OP1 busy using Read Status (05H). + * Suspended State is supported. + */ + enum busy_polling_methods { + POLL_OP2_EXTENDED_STATUS = 0, + POLL_READ_STATUS = 1 + } busy_polling_method; + + unsigned int update_rate; + + /* All times in microsecond (us) */ + unsigned int polling_delay_read_counter_us; + unsigned int polling_short_delay_write_counter_us; + unsigned int polling_long_delay_write_counter_us; + } rpmc_ctx; }; typedef int (*chip_restore_fn_cb_t)(struct flashctx *flash, void *data); diff --git a/include/rpmc.h b/include/rpmc.h new file mode 100644 index 0000000..fa5c46d --- /dev/null +++ b/include/rpmc.h @@ -0,0 +1,117 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2024 Matti Finder + * (written by Matti Finder <matti.finder(a)gmail.com>) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __RPMC_H__ +#define __RPMC_H__ 1 + +#include <stdint.h> +#include "flash.h" // for flashctx + +/** + * @defgroup flashrom-rpmc Write Protect + * @{ + */ + +#define RPMC_OP1_MSG_HEADER_LENGTH 4 +#define RPMC_SIGNATURE_LENGTH 32 +#define RPMC_COUNTER_LENGTH 4 +#define RPMC_KEY_DATA_LENGTH 4 +#define RPMC_TAG_LENGTH 12 +#define RPMC_HMAC_KEY_LENGTH 32 +#define RPMC_TRUNCATED_SIG_LENGTH 28 + +struct rpmc_status_register { + uint8_t status; + unsigned char tag[RPMC_TAG_LENGTH]; + uint32_t counter_data; + unsigned char signature[RPMC_SIGNATURE_LENGTH]; +}; + +/** + * @brief Write root key on flashchip + *q + * @param[in] flash Flash context which rpmc options will be used + * @param[in] keyfile Location of 32-byte key to use + * @param[in] counter_address Address of counter (starts at 0) + * + * @return Rpmc extended status value, or -1 on general error + */ +int rpmc_write_root_key(struct flashrom_flashctx * flash, + const char * const keyfile, + const unsigned int counter_address); + +/** + * @brief Update hmac key register + * + * @param[in] flash Flash context which rpmc options will be used + * @param[in] keyfile Location of 32-byte key to use + * @param[in] key_data 4-bytes of data to use as key data + * @param[in] counter_address Address of counter (starts at 0) + * + * @return Rpmc extended status value, or -1 on general error + */ +int rpmc_update_hmac_key(struct flashrom_flashctx * flash, + const char * const keyfile, + const uint32_t key_data, + const unsigned int counter_address); + +/** + * @brief Increment monotonic counter value + * + * @param[in] flash Flash context which rpmc options will be used + * @param[in] keyfile Location of 32-byte key to use + * @param[in] key_data 4-bytes of data to use as key data + * @param[in] counter_address Address of counter (starts at 0) + * @param[in] previous_value Previous value of counter + * + * @return Rpmc extended status value, or -1 on general error + */ +int rpmc_increment_counter(struct flashrom_flashctx * flash, + const char * const keyfile, + const uint32_t key_data, + const unsigned int counter_address, + const uint32_t previous_value); + +/** + * @brief Get monotonic counter value + * + * @param[in] flash Flash context which rpmc options will be used + * @param[in] keyfile Location of 32-byte key to use + * @param[in] key_data 4-bytes of data to use as key data + * @param[in] counter_address Address of counter (starts at 0) + * @param[out] counter_value Pointer to write the counter value to + * + * @return Rpmc extended status value, or -1 on general error + */ +int rpmc_get_monotonic_counter(struct flashrom_flashctx * flash, + const char * const keyfile, + const uint32_t key_data, + const unsigned int counter_address, + uint32_t * const counter_value); + +/** + * @brief Update hmac key register + * + * @param[in] flash Flash context which rpmc options will be used + * @param[out] status Status register to write data into + * + * @return 0 on success, otherwise 1 + */ +int rpmc_read_data(struct flashrom_flashctx * flash, struct rpmc_status_register * status); + +/** @} */ /* end flashrom-rpmc */ + +#endif /* !__RPMC_H__ */ diff --git a/meson.build b/meson.build index 26d96d9..9cf2ffc 100644 --- a/meson.build +++ b/meson.build @@ -164,6 +164,7 @@ libusb1 = dependency('libusb-1.0', required : group_usb) libftdi1 = dependency('libftdi1', required : group_ftdi) libjaylink = dependency('libjaylink', required : group_jlink, version : '>=0.3.0') +libcrypto = dependency('libcrypto', required : get_option('rpmc'), version : '>=3.0.0') # ECAM is supported in libpci after 3.13.0 if libpci.version().version_compare('>=3.13.0') @@ -172,6 +173,13 @@ add_project_arguments('-DCONFIG_USE_LIBPCI_ECAM=0', language: 'c') endif +# Support additional rpmc commands if libcrypto is installed +if get_option('rpmc').enabled() and libcrypto.found() + add_project_arguments('-DCONFIG_RPMC_ENABLED=1', language : 'c') + srcs += 'rpmc.c' + deps += libcrypto +endif + if host_machine.system() == 'windows' # Specifying an include_path that doesn't exist is an error, # but we only use this if the library is found in the same directory. diff --git a/meson_options.txt b/meson_options.txt index 6df95ba..87456a9 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -24,3 +24,4 @@ option('delay_minimum_sleep_us', type : 'integer', min : 0, value : 100, description : 'Minimum time in microseconds to suspend execution for (rather than polling) when a delay is required.' + ' Larger values may perform better on machines with low timer resolution, at the cost of increased power.') +option('rpmc', type : 'feature', value : 'auto', description : 'Support for Replay Protected Monotonic Counter (RPMC) commands as specified by JESD260') diff --git a/rpmc.c b/rpmc.c new file mode 100644 index 0000000..7f9fcaa --- /dev/null +++ b/rpmc.c @@ -0,0 +1,398 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2024 Matti Finder + * (written by Matti Finder <matti.finder(a)gmail.com>) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "rpmc.h" +#include "flash.h" +#include <stdint.h> +#include <stddef.h> +#include <unistd.h> +#include <openssl/hmac.h> +#include <openssl/evp.h> +#include <openssl/rand.h> +#include <string.h> + +// OP1 commands +#define RPMC_WRITE_ROOT_KEY_MSG_LENGTH (RPMC_OP1_MSG_HEADER_LENGTH + RPMC_HMAC_KEY_LENGTH + RPMC_TRUNCATED_SIG_LENGTH) +#define RPMC_UPDATE_HMAC_KEY_MSG_LENGTH (RPMC_OP1_MSG_HEADER_LENGTH + RPMC_KEY_DATA_LENGTH + RPMC_SIGNATURE_LENGTH) +#define RPMC_INCREMENT_MONOTONIC_COUNTER_MSG_LENGTH (RPMC_OP1_MSG_HEADER_LENGTH + RPMC_COUNTER_LENGTH + RPMC_SIGNATURE_LENGTH) +#define RPMC_GET_MONOTONIC_COUNTER_MSG_LENGTH (RPMC_OP1_MSG_HEADER_LENGTH + RPMC_TAG_LENGTH + RPMC_SIGNATURE_LENGTH) + +// OP2 commands +#define RPMC_READ_DATA_MSG_LENGTH 2 +#define RPMC_READ_DATA_ANSWER_LENGTH (1 + RPMC_TAG_LENGTH + RPMC_COUNTER_LENGTH + RPMC_SIGNATURE_LENGTH) + +static int rpmc_get_extended_status(struct flashrom_flashctx * flash, uint8_t * status) +{ + const unsigned char extended_status_msg[RPMC_READ_DATA_MSG_LENGTH] = { + flash->chip->rpmc_ctx.op2_opcode, + 0 // dummy + }; + + if (spi_send_command(flash, RPMC_READ_DATA_MSG_LENGTH, 1, extended_status_msg, status)) { + msg_gerr("Reading extended status failed\n"); + return 1; + } + + return 0; +} + +static int rpmc_get_extended_status_long(struct flashrom_flashctx * flash, + struct rpmc_status_register * status, + // optional to check values tag and signature against + const unsigned char * const tag, + const unsigned char * const key) +{ + const unsigned int tag_offset = 1; + const unsigned int counter_data_offset = tag_offset + RPMC_TAG_LENGTH; + const unsigned int signature_offset = counter_data_offset + RPMC_COUNTER_LENGTH; + const unsigned char cmd[RPMC_READ_DATA_MSG_LENGTH] = { + flash->chip->rpmc_ctx.op2_opcode, + 0 // dummy + }; + unsigned char answer[RPMC_READ_DATA_ANSWER_LENGTH]; + + int ret = spi_send_command(flash, RPMC_READ_DATA_MSG_LENGTH, RPMC_READ_DATA_ANSWER_LENGTH, cmd, answer); + if (ret) { + msg_gerr("reading extended status failed\n"); + return ret; + } + + status->status = answer[0]; + + memcpy(status->tag, answer + tag_offset, RPMC_TAG_LENGTH); + + status->counter_data = answer[counter_data_offset]; + status->counter_data = (status->counter_data << 8) | answer[counter_data_offset + 1]; + status->counter_data = (status->counter_data << 8) | answer[counter_data_offset + 2]; + status->counter_data = (status->counter_data << 8) | answer[counter_data_offset + 3]; + + memcpy(status->signature, answer + signature_offset, RPMC_SIGNATURE_LENGTH); + + if (tag != NULL) { + if (memcmp(tag, status->tag, RPMC_TAG_LENGTH) != 0) { + msg_gwarn("Tag doesn't match counter might be false\n"); + } + } + + if (key != NULL) { + unsigned char * signature = HMAC(EVP_sha256(), + key, RPMC_HMAC_KEY_LENGTH, + answer + tag_offset, RPMC_TAG_LENGTH + RPMC_COUNTER_LENGTH, + NULL, NULL); + if (signature == NULL) { + msg_gerr("Could not generate signature\n"); + ret = 1; + } else if (memcmp(signature, status->signature, RPMC_SIGNATURE_LENGTH) != 0) { + msg_gwarn("Signature doesn't match, counter might be false\n"); + } + } + + return ret; +} + +static int rpmc_poll_until_finished(struct flashrom_flashctx * flash) +{ + unsigned char poll_response; + + do { + const unsigned char status_poll_msg = 0x05; + + // since we aren't really a time critical application we just sleep for the longest time + if (usleep(flash->chip->rpmc_ctx.polling_long_delay_write_counter_us)) { + msg_gdbg("%s: usleep failed\n", __func__); + } + + switch (flash->chip->rpmc_ctx.busy_polling_method) { + case POLL_READ_STATUS: + if (spi_send_command(flash, 1, 1, &status_poll_msg, &poll_response)) { + msg_gerr("Polling Status-Register-1 failed\n"); + return 1; + } + break; + case POLL_OP2_EXTENDED_STATUS: + if (rpmc_get_extended_status(flash, &poll_response)) { + return 1; + } + break; + default: + msg_gerr("Unsupported busy polling method found, this should not happen. Exiting...\n"); + return 1; + } + } while ((poll_response & 1) != 0); + + return 0; +} + +static int rpmc_calculate_hmac_key_register(const char * const keyfile, + const uint32_t key_data, + unsigned char * hmac_key_register) +{ + unsigned char key[RPMC_HMAC_KEY_LENGTH]; + unsigned char key_data_buf[RPMC_KEY_DATA_LENGTH]; + key_data_buf[0] = (key_data >> 24) & 0xff; + key_data_buf[1] = (key_data >> 16) & 0xff; + key_data_buf[2] = (key_data >> 8) & 0xff; + key_data_buf[3] = key_data & 0xff; + + if (keyfile == NULL || read_buf_from_file(key, RPMC_HMAC_KEY_LENGTH, keyfile) != 0) { + return 1; + } + + unsigned char * key_ptr = HMAC(EVP_sha256(), + key, RPMC_HMAC_KEY_LENGTH, + key_data_buf, RPMC_KEY_DATA_LENGTH, + hmac_key_register, NULL); + if (key_ptr == NULL) { + msg_gerr("Could not calculate HMAC signature for hmac storage\n"); + return 1; + } + + return 0; +} + +static int rpmc_basic_checks(struct flashrom_flashctx * flash, const unsigned int counter_address) +{ + if ((flash->chip->feature_bits & FEATURE_FLASH_HARDENING) == 0) { + msg_gerr("Flash hardening is not supported on this chip, aborting.\n"); + return 1; + } + + if (counter_address >= flash->chip->rpmc_ctx.num_counters) { + msg_gerr("Counter address is not in range, should be between 0 and %d.\n", + flash->chip->rpmc_ctx.num_counters - 1); + return 1; + } + + return 0; +} + +static int rpmc_send_and_wait(struct flashrom_flashctx * flash, + const unsigned char * const msg, + const size_t length) +{ + msg_gdbg("sending rpmc command\n"); + int ret = spi_send_command(flash, length, 0, msg, NULL); + if (ret) + return ret; + + // check operation status + ret = rpmc_poll_until_finished(flash); + if (ret) + return ret; + + msg_gdbg("done sending rpmc command\n"); + + return 0; +} + +static int rpmc_sign_send_wait_check(struct flashrom_flashctx * flash, + unsigned char * const msg, + const size_t msg_length, + const size_t signature_offset, + const char * const keyfile, + const uint32_t key_data) +{ + unsigned char hmac_key_register[RPMC_HMAC_KEY_LENGTH]; + + if (rpmc_calculate_hmac_key_register(keyfile, key_data, hmac_key_register)) { + return -1; + } + + if (HMAC(EVP_sha256(), + hmac_key_register, RPMC_HMAC_KEY_LENGTH, + msg, signature_offset, + msg + signature_offset, NULL) == NULL) { + msg_gerr("Could not generate HMAC signature\n"); + return -1; + } + + if (rpmc_send_and_wait(flash, msg, msg_length)) { + return -1; + } + + uint8_t return_status; + if (rpmc_get_extended_status(flash, &return_status)){ + return -1; + } + + return return_status; +} + +int rpmc_write_root_key(struct flashrom_flashctx * flash, + const char * const keyfile, + const unsigned int counter_address) +{ + const unsigned int key_offset = RPMC_OP1_MSG_HEADER_LENGTH; + const unsigned int signature_offset = key_offset + RPMC_HMAC_KEY_LENGTH; + const unsigned int signature_cutoff = RPMC_SIGNATURE_LENGTH - RPMC_TRUNCATED_SIG_LENGTH; + + unsigned char msg[RPMC_WRITE_ROOT_KEY_MSG_LENGTH]; + msg[0] = flash->chip->rpmc_ctx.op1_opcode; // Opcode + msg[1] = 0x00; // CmdType + msg[2] = counter_address; // CounterAddr + msg[3] = 0; // Reserved + + if (rpmc_basic_checks(flash, counter_address)) { + return -1; + } + + if (keyfile == NULL || + read_buf_from_file(msg + key_offset, RPMC_HMAC_KEY_LENGTH, keyfile) != 0) { + return -1; + } + + unsigned char * signature = HMAC(EVP_sha256(), + msg + key_offset, RPMC_HMAC_KEY_LENGTH, + msg, RPMC_OP1_MSG_HEADER_LENGTH, + NULL, NULL); + if (signature == NULL) { + msg_gerr("Could not calculate HMAC signature for message\n"); + return -1; + } + + // need to truncate the signature a bit + memcpy(msg + signature_offset, signature + signature_cutoff, RPMC_TRUNCATED_SIG_LENGTH); + + if (rpmc_send_and_wait(flash, msg, RPMC_WRITE_ROOT_KEY_MSG_LENGTH)) { + return -1; + } + + uint8_t return_status; + if (rpmc_get_extended_status(flash, &return_status)){ + return -1; + } + + return return_status; +} + +int rpmc_update_hmac_key(struct flashrom_flashctx * flash, + const char * const keyfile, + const uint32_t key_data, + const unsigned int counter_address) +{ + const unsigned int signature_offset = RPMC_OP1_MSG_HEADER_LENGTH + RPMC_KEY_DATA_LENGTH; + unsigned char msg[RPMC_UPDATE_HMAC_KEY_MSG_LENGTH]; + msg[0] = flash->chip->rpmc_ctx.op1_opcode; // Opcode + msg[1] = 0x01; // CmdType + msg[2] = counter_address; // CounterAddr + msg[3] = 0; // Reserved + msg[4] = (key_data >> 24) & 0xff; + msg[5] = (key_data >> 16) & 0xff; + msg[6] = (key_data >> 8) & 0xff; + msg[7] = key_data & 0xff; + + if (rpmc_basic_checks(flash, counter_address)) { + return -1; + } + + return rpmc_sign_send_wait_check(flash, msg, RPMC_UPDATE_HMAC_KEY_MSG_LENGTH, + signature_offset, keyfile, key_data); +} + +int rpmc_increment_counter(struct flashrom_flashctx * flash, + const char * const keyfile, + const uint32_t key_data, + const unsigned int counter_address, + const uint32_t previous_value) +{ + const unsigned int signature_offset = RPMC_OP1_MSG_HEADER_LENGTH + RPMC_COUNTER_LENGTH; + unsigned char msg[RPMC_INCREMENT_MONOTONIC_COUNTER_MSG_LENGTH]; + msg[0] = flash->chip->rpmc_ctx.op1_opcode; // Opcode + msg[1] = 0x02; // CmdType + msg[2] = counter_address; // CounterAddr + msg[3] = 0; // Reserved + // CounterData + msg[4] = (previous_value >> 24) & 0xff; + msg[5] = (previous_value >> 16) & 0xff; + msg[6] = (previous_value >> 8) & 0xff; + msg[7] = previous_value & 0xff; + + if (rpmc_basic_checks(flash, counter_address)) { + return 1; + } + + return rpmc_sign_send_wait_check(flash, msg, RPMC_INCREMENT_MONOTONIC_COUNTER_MSG_LENGTH, + signature_offset, keyfile, key_data); +} + +int rpmc_get_monotonic_counter(struct flashrom_flashctx * flash, + const char * const keyfile, + const uint32_t key_data, + const unsigned int counter_address, + uint32_t * const counter_value) +{ + unsigned char hmac_key_register[RPMC_HMAC_KEY_LENGTH]; + const unsigned int tag_offset = RPMC_OP1_MSG_HEADER_LENGTH; + const unsigned int signature_offset = tag_offset + RPMC_TAG_LENGTH; + unsigned char msg[RPMC_GET_MONOTONIC_COUNTER_MSG_LENGTH]; + msg[0] = flash->chip->rpmc_ctx.op1_opcode; // Opcode + msg[1] = 0x03; // CmdType + msg[2] = counter_address; // CounterAddr + msg[3] = 0; // Reserved + + if (rpmc_basic_checks(flash, counter_address)) { + return -1; + } + + if (RAND_bytes(msg + tag_offset, RPMC_TAG_LENGTH) != 1) { + msg_gerr("Could not generate random tag.\n"); + return -1; + } + + msg_gdbg("Random tag is:"); + for (size_t i = 0; i < RPMC_TAG_LENGTH; i++) { + msg_gdbg(" 0x%02x", msg[tag_offset + i]); + } + msg_gdbg("\n"); + + if (rpmc_calculate_hmac_key_register(keyfile, key_data, hmac_key_register)) { + return -1; + } + + if (HMAC(EVP_sha256(), + hmac_key_register, RPMC_HMAC_KEY_LENGTH, + msg, signature_offset, + msg + signature_offset, NULL) == NULL) { + msg_gerr("Could not generate HMAC signature\n"); + return -1; + } + + if (rpmc_send_and_wait(flash, msg, RPMC_GET_MONOTONIC_COUNTER_MSG_LENGTH)) { + return -1; + } + + struct rpmc_status_register status; + if (rpmc_get_extended_status_long(flash, &status, msg + tag_offset, hmac_key_register)) { + return -1; + } + + *counter_value = status.counter_data; + return status.status; +} + +int rpmc_read_data(struct flashrom_flashctx * flash, struct rpmc_status_register * status) +{ + // hack around not having a counter address + if (rpmc_basic_checks(flash, 0)) { + return 1; + } + + if (rpmc_get_extended_status_long(flash, status, NULL, NULL)) { + return 1; + } + + return 0; +} diff --git a/sfdp.c b/sfdp.c index 8683779..110738c 100644 --- a/sfdp.c +++ b/sfdp.c @@ -252,6 +252,88 @@ return 0; } +static unsigned int bits_to_counter_delay(const uint8_t bits) +{ + unsigned int value = bits & 0xf; + + switch ((bits & (0b11 << 4)) >> 4) { + case 0b00: + value *= 1; + break; + case 0b01: + value *= 16; + break; + case 0b10: + value *= 128; + break; + case 0b11: + value *= 1000; + break; + } + + return value; +} + +static int parse_rpmc_parameter_table(struct flashchip * const chip, const uint8_t * const buf, const uint16_t len) +{ + if (len != 2 * 4) { + msg_cdbg("Length of RPMC parameter table is wrong, skipping it\n"); + return 1; + } + + msg_cdbg("Parsing rpmc parameter table...\n"); + + // first dword + uint32_t first_dword = ((unsigned int)buf[(4 * 0) + 0]); + first_dword |= ((unsigned int)buf[(4 * 0) + 1]) << 8; + first_dword |= ((unsigned int)buf[(4 * 0) + 2]) << 16; + first_dword |= ((unsigned int)buf[(4 * 0) + 3]) << 24; + + if ((first_dword & 0b1) != 0) { + // flash hardening is not supported + msg_cdbg("Flash Hardening not supported\n"); + goto done; + } + + chip->feature_bits |= FEATURE_FLASH_HARDENING; + + chip->rpmc_ctx.busy_polling_method = (first_dword & (1 << 2)) >> 2; + msg_cspew("Busy polling method: %u\n", chip->rpmc_ctx.busy_polling_method); + + chip->rpmc_ctx.num_counters = ((first_dword & (0xf << 4)) >> 4) + 1; + msg_cspew("Number of counters: %u\n", chip->rpmc_ctx.num_counters); + + chip->rpmc_ctx.op1_opcode = (first_dword & (0xff << 8)) >> 8; + msg_cspew("OP1 opcode: 0x%02x\n", chip->rpmc_ctx.op1_opcode); + + chip->rpmc_ctx.op2_opcode = (first_dword & (0xff << 16)) >> 16; + msg_cspew("OP2 opcode: 0x%02x\n", chip->rpmc_ctx.op2_opcode); + + chip->rpmc_ctx.update_rate = 5 * (1 << ((first_dword & (0xf << 24)) >> 24)); + msg_cspew("Update rate: %u seconds\n", chip->rpmc_ctx.update_rate); + + // second dword + uint32_t second_dword = ((unsigned int)buf[(4 * 1) + 0]); + second_dword |= ((unsigned int)buf[(4 * 1) + 1]) << 8; + second_dword |= ((unsigned int)buf[(4 * 1) + 2]) << 16; + second_dword |= ((unsigned int)buf[(4 * 1) + 3]) << 24; + + chip->rpmc_ctx.polling_delay_read_counter_us = bits_to_counter_delay(second_dword & 0xf); + msg_cspew("Read counter polling delay: %u us\n", chip->rpmc_ctx.polling_delay_read_counter_us); + + chip->rpmc_ctx.polling_short_delay_write_counter_us = bits_to_counter_delay((second_dword >> 8) & 0xf); + msg_cspew("Write counter short polling delay: %u us\n", + chip->rpmc_ctx.polling_short_delay_write_counter_us); + + chip->rpmc_ctx.polling_long_delay_write_counter_us = bits_to_counter_delay((second_dword >> 16) & 0xf) * 1000; + msg_cspew("Write counter long polling delay: %u us\n", + chip->rpmc_ctx.polling_long_delay_write_counter_us); + +done: + msg_cdbg("done.\n"); + return 0; +} + int probe_spi_sfdp(struct flashctx *flash) { int ret = 0; @@ -359,23 +441,37 @@ } msg_cspew("\n"); - if (i == 0) { /* Mandatory JEDEC SFDP parameter table */ - if (hdrs[i].id != 0) - msg_cdbg("ID of the mandatory JEDEC SFDP " - "parameter table is not 0 as demanded " - "by JESD216 (warning only).\n"); - if (hdrs[i].v_major != 0x01) { - msg_cdbg("The chip contains an unknown " - "version of the JEDEC flash " - "parameters table, skipping it.\n"); - } else if (len != 4 * 4 && len < 9 * 4) { - msg_cdbg("Length of the mandatory JEDEC SFDP " - "parameter table is wrong (%d B), " - "skipping it.\n", len); - } else if (sfdp_fill_flash(flash->chip, tbuf, len) == 0) - ret = 1; + // TODO: implement parsing for other pages + switch (hdrs[i].id){ + case 0: // Mandatory JEDEC SFDP parameter table + if (hdrs[i].v_major != 0x01) { + msg_cdbg("The chip contains an unknown " + "version of the JEDEC flash " + "parameters table, skipping it.\n"); + } else if (len != 4 * 4 && len < 9 * 4) { + msg_cdbg("Length of the mandatory JEDEC SFDP " + "parameter table is wrong (%d B), " + "skipping it.\n", len); + } else if (sfdp_fill_flash(flash->chip, tbuf, len) == 0) { + ret = 1; + } + break; + case 0x03: // RPMC parameter table as specified in JESD260 + if (hdrs[i].v_major != 1) { + msg_cdbg("The chip contains an unknown " + "version of the JEDEC flash " + "parameters table, skipping it.\n"); + } else if (parse_rpmc_parameter_table(flash->chip, tbuf, len) == 0) { + ret = 1; + } + break; + default: + msg_cdbg("Support for SFDP Page with ID 0x%02x not implemented, skipping it.\n", + hdrs[i].id); + break; } + free(tbuf); } -- To view, visit https://review.coreboot.org/c/flashrom/+/84934?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6ab3d0446e9fd674b20550fdbfaf499b8d4a9b38 Gerrit-Change-Number: 84934 Gerrit-PatchSet: 1 Gerrit-Owner: Matti Finder <matti.finder(a)gmail.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org>

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flashrom-gerrit October 2024