March 2023 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: buspirate: Add option for setting the aux pin
by Sean Anderson (Code Review) 13 Apr '23

13 Apr '23

Sean Anderson has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43608 ) Change subject: buspirate: Add option for setting the aux pin ...................................................................... buspirate: Add option for setting the aux pin This adds a parameter to drive the aux pin low (or high if you explicitly want the previous behavior). Some boards need to have a reset pin driven low before the firmware can be safely flashed. With the Bus Pirate, this is most easily done with the auxiliary pin. Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775 Signed-off-by: Sean Anderson <seanga2(a)gmail.com> --- M buspirate_spi.c M flashrom.8.tmpl 2 files changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/43608/1 diff --git a/buspirate_spi.c b/buspirate_spi.c index fdfc0e4..1ccb107 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -228,6 +228,7 @@ int serialspeed_index = -1; int ret = 0; int pullup = 0; + int aux = 1; dev = extract_programmer_param("dev"); if (dev && !strlen(dev)) { @@ -277,6 +278,17 @@ } free(tmp); + tmp = extract_programmer_param("aux"); + if (tmp) { + if (strcasecmp("high", tmp) == 0) + ; /* Default */ + else if (strcasecmp("low", tmp) == 0) + aux = 0; + else + msg_perr("Invalid AUX state, driving high by default.\n"); + } + free(tmp); + /* Default buffer size is 19: 16 bytes data, 3 bytes control. */ #define DEFAULT_BUFSIZE (16 + 3) bp_commbuf = malloc(DEFAULT_BUFSIZE); @@ -520,11 +532,18 @@ } /* Initial setup (SPI peripherals config): Enable power, CS high, AUX */ - bp_commbuf[0] = 0x40 | 0x0b; + bp_commbuf[0] = 0x40 | 0x09; if (pullup == 1) { bp_commbuf[0] |= (1 << 2); msg_pdbg("Enabling pull-up resistors.\n"); } + if (aux) { + bp_commbuf[0] |= (1 << 1); + msg_pdbg("Driving AUX high.\n"); + } else { + msg_pdbg("Driving AUX low.\n"); + } + ret = buspirate_sendrecv(bp_commbuf, 1, 1); if (ret) return 1; diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index db50d59..caf860c 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -902,6 +902,19 @@ .URLB "http://dangerousprototypes.com/docs/Practical_guide_to_Bus_Pirate_pull-up_r…" \ "in a guide by dangerousprototypes" . Only the external supply voltage (Vpu) is supported as of this writing. +.sp +An optional aux parameter specifies the state of the Bus Pirate auxiliary pin. +This may be used to drive the auxiliary pin high or low before a transfer. +Syntax is +.sp +.B " flashrom -p buspirate_spi:aux=state" +.sp +where +.B state +can be +.BR high " or " low . +The default +.BR state " is " high . .SS .BR "pickit2_spi " programmer .IP -- To view, visit https://review.coreboot.org/c/flashrom/+/43608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775 Gerrit-Change-Number: 43608 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Anderson <seanga2(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: util/flashchips_db_jsoniser: Fix bug
by Edward O'Callaghan (Code Review) 30 Mar '23

30 Mar '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/74083 ) Change subject: util/flashchips_db_jsoniser: Fix bug ...................................................................... util/flashchips_db_jsoniser: Fix bug Spotted-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: Ie514f512b5299290a253a56e950c30127e55ca84 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M util/flashchips_db_jsoniser/main.c 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/74083/1 diff --git a/util/flashchips_db_jsoniser/main.c b/util/flashchips_db_jsoniser/main.c index 2366296..a1eda3f 100644 --- a/util/flashchips_db_jsoniser/main.c +++ b/util/flashchips_db_jsoniser/main.c @@ -172,7 +172,7 @@ if (j) printf(",\n"); printf("\t\t\t\t\t\t\t{\n"); printf("\t\t\t\t\t\t\t\t\"size\": %d,\n", block.size); - printf("\t\t\t\t\t\t\t\t\"count\": %d\n", block.size); + printf("\t\t\t\t\t\t\t\t\"count\": %d\n", block.count); printf("\t\t\t\t\t\t\t}"); } printf("\t\t\t\t\t\t],\n"); -- To view, visit https://review.coreboot.org/c/flashrom/+/74083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie514f512b5299290a253a56e950c30127e55ca84 Gerrit-Change-Number: 74083 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[XL] Change in flashrom[master]: data/flashchips.json: Add JSON flashchips db variant
by Edward O'Callaghan (Code Review) 30 Mar '23

30 Mar '23

Attention is currently required from: Thomas Heijligen, Angel Pons. Hello build bot (Jenkins), Thomas Heijligen, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/74071 to look at the new patch set (#3). Change subject: data/flashchips.json: Add JSON flashchips db variant ...................................................................... data/flashchips.json: Add JSON flashchips db variant Generated from flashchips.c at commit 73e47091. Change-Id: I7fceac8a285c8ecf3f3a09a90cc1ae369e8a9429 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- A data/flashchips.json 1 file changed, 177,912 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/74071/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/74071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7fceac8a285c8ecf3f3a09a90cc1ae369e8a9429 Gerrit-Change-Number: 74071 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in flashrom[master]: util/flashchips_db_jsoniser: Initial version
by Angel Pons (Code Review) 29 Mar '23

29 Mar '23

Attention is currently required from: Thomas Heijligen, Edward O'Callaghan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/74065 ) Change subject: util/flashchips_db_jsoniser: Initial version ...................................................................... Patch Set 1: (1 comment) File util/flashchips_db_jsoniser/main.c: https://review.coreboot.org/c/flashrom/+/74065/comment/2303093a_53b419d1 PS1, Line 69: static char *decode_test_state(enum test_state ts) : { : switch (ts) { : case OK: return "OK"; : case NT: return "NT"; : case BAD: return "BAD"; : case DEP: return "DEP"; : case NA: return "NA"; : } : return NULL; : }; : : static char *decode_cmdset(int cmdset) : { : switch (cmdset) { : case SPI25: return "SPI25"; : case SPI_EDI: return "SPI_EDI"; : } : return NULL; : } > No. […] Ack -- To view, visit https://review.coreboot.org/c/flashrom/+/74065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3b65caeb811ec0978091c543ccffb5a1b0d254ba Gerrit-Change-Number: 74065 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sam McNally <sammc(a)google.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Wed, 29 Mar 2023 10:45:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in flashrom[master]: util/flashchips_db_jsoniser: Initial version
by Edward O'Callaghan (Code Review) 29 Mar '23

29 Mar '23

Attention is currently required from: Thomas Heijligen, Angel Pons. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/74065 ) Change subject: util/flashchips_db_jsoniser: Initial version ...................................................................... Patch Set 1: (1 comment) File util/flashchips_db_jsoniser/main.c: https://review.coreboot.org/c/flashrom/+/74065/comment/352ffa23_d4769747 PS1, Line 69: static char *decode_test_state(enum test_state ts) : { : switch (ts) { : case OK: return "OK"; : case NT: return "NT"; : case BAD: return "BAD"; : case DEP: return "DEP"; : case NA: return "NA"; : } : return NULL; : }; : : static char *decode_cmdset(int cmdset) : { : switch (cmdset) { : case SPI25: return "SPI25"; : case SPI_EDI: return "SPI_EDI"; : } : return NULL; : } > Ah, so this won't be needed No. This specific code is irrelevant for anything more than showing that the array of C struct's into JSON transformation is genuine so the community can audit and modify it until we are happy with the JSON output adequately represents the original with good fidelity. If you wish you can clang-format it locally for your own readability, but I don't want to break output formatting for no reason. -- To view, visit https://review.coreboot.org/c/flashrom/+/74065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3b65caeb811ec0978091c543ccffb5a1b0d254ba Gerrit-Change-Number: 74065 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sam McNally <sammc(a)google.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 29 Mar 2023 10:15:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in flashrom[master]: util/flashchips_db_jsoniser: Initial version
by Angel Pons (Code Review) 29 Mar '23

29 Mar '23

Attention is currently required from: Thomas Heijligen, Edward O'Callaghan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/74065 ) Change subject: util/flashchips_db_jsoniser: Initial version ...................................................................... Patch Set 1: (1 comment) File util/flashchips_db_jsoniser/main.c: https://review.coreboot.org/c/flashrom/+/74065/comment/335cd670_759f0df7 PS1, Line 69: static char *decode_test_state(enum test_state ts) : { : switch (ts) { : case OK: return "OK"; : case NT: return "NT"; : case BAD: return "BAD"; : case DEP: return "DEP"; : case NA: return "NA"; : } : return NULL; : }; : : static char *decode_cmdset(int cmdset) : { : switch (cmdset) { : case SPI25: return "SPI25"; : case SPI_EDI: return "SPI_EDI"; : } : return NULL; : } > I only shared this to show the result is reproducible. This code is a means to a end. Ah, so this won't be needed -- To view, visit https://review.coreboot.org/c/flashrom/+/74065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3b65caeb811ec0978091c543ccffb5a1b0d254ba Gerrit-Change-Number: 74065 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sam McNally <sammc(a)google.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Wed, 29 Mar 2023 10:08:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in flashrom[master]: flashchips.c: Drop 'unlock' func for chips with WP topologies
by Edward O'Callaghan (Code Review) 29 Mar '23

29 Mar '23

Attention is currently required from: Angel Pons, Nikolai Artemiev. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/73714 ) Change subject: flashchips.c: Drop 'unlock' func for chips with WP topologies ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/73714/comment/d2bdef62_cd548119 PS3, Line 10: boutique > What does "boutique" mean in this context? A special selection of merchandise and accessories for each chip rather than a completely qualified description of the status registers that the writeprotect framework confers. -- To view, visit https://review.coreboot.org/c/flashrom/+/73714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib24e91b28cb3d87ba74019e23f88209b95a21c5d Gerrit-Change-Number: 73714 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 29 Mar 2023 09:46:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in flashrom[master]: util/flashchips_db_jsoniser: Initial version
by Edward O'Callaghan (Code Review) 29 Mar '23

29 Mar '23

Attention is currently required from: Thomas Heijligen, Angel Pons. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/74065 ) Change subject: util/flashchips_db_jsoniser: Initial version ...................................................................... Patch Set 1: (1 comment) File util/flashchips_db_jsoniser/main.c: https://review.coreboot.org/c/flashrom/+/74065/comment/98bafcaf_0aeed9b7 PS1, Line 69: static char *decode_test_state(enum test_state ts) : { : switch (ts) { : case OK: return "OK"; : case NT: return "NT"; : case BAD: return "BAD"; : case DEP: return "DEP"; : case NA: return "NA"; : } : return NULL; : }; : : static char *decode_cmdset(int cmdset) : { : switch (cmdset) { : case SPI25: return "SPI25"; : case SPI_EDI: return "SPI_EDI"; : } : return NULL; : } > That doesn't matter. We are going to put this in the bin after we got the output. I only shared this to show the result is reproducible. This code is a means to a end. -- To view, visit https://review.coreboot.org/c/flashrom/+/74065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3b65caeb811ec0978091c543ccffb5a1b0d254ba Gerrit-Change-Number: 74065 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sam McNally <sammc(a)google.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 29 Mar 2023 09:44:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in flashrom[master]: util/flashchips_db_jsoniser: Initial version
by Edward O'Callaghan (Code Review) 29 Mar '23

29 Mar '23

Attention is currently required from: Thomas Heijligen, Angel Pons. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/74065 ) Change subject: util/flashchips_db_jsoniser: Initial version ...................................................................... Patch Set 1: (1 comment) File util/flashchips_db_jsoniser/main.c: https://review.coreboot.org/c/flashrom/+/74065/comment/3c0ac95b_e9b52fc6 PS1, Line 69: static char *decode_test_state(enum test_state ts) : { : switch (ts) { : case OK: return "OK"; : case NT: return "NT"; : case BAD: return "BAD"; : case DEP: return "DEP"; : case NA: return "NA"; : } : return NULL; : }; : : static char *decode_cmdset(int cmdset) : { : switch (cmdset) { : case SPI25: return "SPI25"; : case SPI_EDI: return "SPI_EDI"; : } : return NULL; : } > Indentation: please use tabs instead of spaces That doesn't matter. We are going to put this in the bin after we got the output. -- To view, visit https://review.coreboot.org/c/flashrom/+/74065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3b65caeb811ec0978091c543ccffb5a1b0d254ba Gerrit-Change-Number: 74065 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sam McNally <sammc(a)google.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 29 Mar 2023 09:41:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in flashrom[master]: util/flashchips_db_jsoniser: Add wp decoding
by Edward O'Callaghan (Code Review) 29 Mar '23

29 Mar '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/74074 ) Change subject: util/flashchips_db_jsoniser: Add wp decoding ...................................................................... util/flashchips_db_jsoniser: Add wp decoding Change-Id: I4badbdbf5a5745f1e7de17b72136dee1ef791d76 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M util/flashchips_db_jsoniser/main.c 1 file changed, 115 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/74074/1 diff --git a/util/flashchips_db_jsoniser/main.c b/util/flashchips_db_jsoniser/main.c index 829e58e..2366296 100644 --- a/util/flashchips_db_jsoniser/main.c +++ b/util/flashchips_db_jsoniser/main.c @@ -223,6 +223,107 @@ return NULL; } + +static char *decode_flash_reg(enum flash_reg reg) +{ + switch (reg) { + case INVALID_REG: return "INVALID_REG"; + case STATUS1: return "STATUS1"; + case STATUS2: return "STATUS2"; + case STATUS3: return "STATUS3"; + case SECURITY: return "SECURITY"; + case CONFIG: return "CONFIG"; + case MAX_REGISTERS: return "MAX_REGISTERS"; + } + return NULL; +}; + +static char *decode_writability(int w) +{ + switch (w) { + case RO: return "RO"; + case RW: return "RW"; + case OTP: return "OTP"; + } + return NULL; +} + +static void decode_reg_bit_info(const char *name, struct reg_bit_info info, bool indent) +{ + if (indent) putchar('\t'); + if (name) printf("\t\"%s\": {\n", name); else printf("\t{\n"); + + if (indent) putchar('\t'); + /* Register containing the bit */ + printf("\t\t\"reg\": \"%s\",\n", decode_flash_reg(info.reg)); + + if (indent) putchar('\t'); + /* Bit index within register */ + printf("\t\t\"bit_index\": %d,\n", info.bit_index); + + if (indent) putchar('\t'); + /* + * Writability of the bit. RW does not guarantee the bit will be + * writable, for example if status register protection is enabled. + */ + printf("\t\t\"writability\": \"%s\"\n", decode_writability(info.writability)); + + if (indent) putchar('\t'); + printf("\t}"); +}; + +static void decode_reg_bit_map(struct reg_bit_map map) +{ + printf("\"reg_bits\": {\n"); + + /* Status register protection bit (SRP) */ + decode_reg_bit_info("srp", map.srp, false); + printf(",\n"); + + /* Status register lock bit (SRP) */ + decode_reg_bit_info("srl", map.srl, false); + printf(",\n"); + + /* + * Note: some datasheets refer to configuration bits that + * function like TB/SEC/CMP bits as BP bits (e.g. BP3 for a bit + * that functions like TB). + * + * As a convention, any config bit that functions like a + * TB/SEC/CMP bit should be assigned to the respective + * tb/sec/cmp field in this structure, even if the datasheet + * uses a different name. + */ + + /* Block protection bits (BP) */ + /* Extra element for terminator */ +//struct reg_bit_info bp[MAX_BP_BITS + 1]; + printf("\t\"bp\": [\n"); + for (unsigned int i = 0; i < MAX_BP_BITS + 1; i++) { + if (i) printf(",\n"); + decode_reg_bit_info(NULL, map.bp[i], true); + } + printf("\n\t],\n"); + + /* Top/bottom protection bit (TB) */ + decode_reg_bit_info("tb", map.tb, false); + printf(",\n"); + + /* Sector/block protection bit (SEC) */ + decode_reg_bit_info("srp", map.srp, false); + printf(",\n"); + + /* Complement bit (CMP) */ + decode_reg_bit_info("cmp", map.cmp, false); + printf(",\n"); + + /* Write Protect Selection (per sector protection when set) */ + decode_reg_bit_info("wps", map.wps, false); + printf("\n"); + + printf("}\n"); +} + int main() { printf("{\n\t\t\"flashchips\": [\n"); @@ -287,10 +388,13 @@ printf("\t\t\t\t\"voltage\": [\n"); printf("\t\t\t\t\t{ \"min\": %d },\n", flashchips[i].voltage.min); printf("\t\t\t\t\t{ \"max\": %d }\n", flashchips[i].voltage.max); - printf("\t\t\t\t]\n"); + printf("\t\t\t\t],\n"); // enum write_granularity gran; + // reg_bits + decode_reg_bit_map(flashchips[i].reg_bits); + printf("\n\t\t\t}\n"); } -- To view, visit https://review.coreboot.org/c/flashrom/+/74074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4badbdbf5a5745f1e7de17b72136dee1ef791d76 Gerrit-Change-Number: 74074 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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