February 2023 - flashrom-gerrit

[XL] Change in flashrom[master]: move manpage to sphinx
by Thomas Heijligen (Code Review) 13 Feb '23

13 Feb '23

Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72619 ) Change subject: move manpage to sphinx ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Waiting on https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/FPA4… -- To view, visit https://review.coreboot.org/c/flashrom/+/72619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iee9f1164c5913e47385e6f7d51dc7775a58b5a67 Gerrit-Change-Number: 72619 Gerrit-PatchSet: 6 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Mon, 13 Feb 2023 17:45:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in flashrom[master]: Add missing Intel B460 flash chip id
by ChrisEric1 CECL (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: Paul Menzel, Nicholas Chin. ChrisEric1 CECL has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72056 ) Change subject: Add missing Intel B460 flash chip id ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/72056/comment/3d6e8404_7853c468 PS4, Line 7: Add missing Intel B460 flash chip id. > Nit: Please also remove the dot/period at the end [1]. […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/72056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id8fcb59d5dbafea3e79c4e3ad75484bbd163feca Gerrit-Change-Number: 72056 Gerrit-PatchSet: 5 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Feb 2023 17:38:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in flashrom[master]: Add support for VIA VL805 USB 3 XHCI flashing
by ChrisEric1 CECL (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: Thomas Heijligen, Nicholas Chin. ChrisEric1 CECL has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72057 ) Change subject: Add support for VIA VL805 USB 3 XHCI flashing ...................................................................... Patch Set 9: (1 comment) File flashrom.8.tmpl: https://review.coreboot.org/c/flashrom/+/72057/comment/1488294d_a688da13 PS8, Line 1706: and raw memory access > pci configutation space is enough. Fixed. -- To view, visit https://review.coreboot.org/c/flashrom/+/72057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I71435afcacdf97e14d627e35bce3d29de9657f38 Gerrit-Change-Number: 72057 Gerrit-PatchSet: 9 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Feb 2023 17:37:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: comment

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[M] Change in flashrom[master]: Add support for VIA VL805 USB 3 XHCI flashing
by ChrisEric1 CECL (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: Thomas Heijligen, Nicholas Chin. ChrisEric1 CECL has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72057 ) Change subject: Add support for VIA VL805 USB 3 XHCI flashing ...................................................................... Patch Set 9: (4 comments) Patchset: PS3: > 1. Ok, […] Ok, I added vl805 to meson_options.txt next to usbblaster File flashchips.c: https://review.coreboot.org/c/flashrom/+/72057/comment/4755d2e2_475f1c34 PS8, Line 19126: .probe = PROBE_SPI_RDID4, > This should also be an other commit. Can be before this or after. I'll take it off, but if this is needed, I will just put it into it's own commit for the Pi. File vl805.c: https://review.coreboot.org/c/flashrom/+/72057/comment/5e9f3b30_40301652 PS3, Line 38: static struct pci_dev *dev = NULL; > This was referred to `static struct pci_dev *dev = NULL`, not `dev_entries`. […] Still lost on what you are trying to say, did you mean flashctx instead of flashxtx? I really hate to ask but can you give a example on what you are trying to say? https://review.coreboot.org/c/flashrom/+/72057/comment/890141e0_adf3208a PS3, Line 72: uint32_t indata = 0; : unsigned int curwritecnt = 0; : unsigned int curreadcnt = 0; > The ` = 0` is not needed for each of them. A declaration of those variables is sufficient. […] Fixed. I removed the " = 0;" with ";" instead. -- To view, visit https://review.coreboot.org/c/flashrom/+/72057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I71435afcacdf97e14d627e35bce3d29de9657f38 Gerrit-Change-Number: 72057 Gerrit-PatchSet: 9 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Feb 2023 17:37:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Comment-In-Reply-To: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: comment

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[M] Change in flashrom[master]: Add support for VIA VL805 USB 3 XHCI flashing
by ChrisEric1 CECL (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: ChrisEric1 CECL, Nicholas Chin. Hello build bot (Jenkins), Thomas Heijligen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/72057 to look at the new patch set (#9). Change subject: Add support for VIA VL805 USB 3 XHCI flashing ...................................................................... Add support for VIA VL805 USB 3 XHCI flashing It works fine for me on my Raspberry Pi 4 Model B. Was able read read, erase, write, verify. Only thing is the WP with the W25X10 gives a untested warning. And I changed W25X10 to RDID4 since it wouldn't work otherwise. Change-Id: I71435afcacdf97e14d627e35bce3d29de9657f38 Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- M Makefile M flashrom.8.tmpl M include/programmer.h M meson.build M meson_options.txt M programmer_table.c A vl805.c 7 files changed, 216 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/57/72057/9 -- To view, visit https://review.coreboot.org/c/flashrom/+/72057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I71435afcacdf97e14d627e35bce3d29de9657f38 Gerrit-Change-Number: 72057 Gerrit-PatchSet: 9 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: Add missing Intel B460 flash chip id
by ChrisEric1 CECL (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: ChrisEric1 CECL, Nicholas Chin. Hello build bot (Jenkins), Paul Menzel, Thomas Heijligen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/72056 to look at the new patch set (#5). Change subject: Add missing Intel B460 flash chip id ...................................................................... Add missing Intel B460 flash chip id Note that while I can read the chip, on my Lenovo Legion T5 28IMB05, cannot write to the flash chip with any tools except upgrading with vendor tool, no downgrades are allowed, due to the fact of SMM, even if I did manage to flash the BIOS chip somehow, would still face bootguard since this machine has bootguard. But if I read the chip, and verify my read bin file, it works fine, until changing the SMBIOS, which is in the vendor BIOS update package. Change-Id: Id8fcb59d5dbafea3e79c4e3ad75484bbd163feca Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- M chipset_enable.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/56/72056/5 -- To view, visit https://review.coreboot.org/c/flashrom/+/72056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id8fcb59d5dbafea3e79c4e3ad75484bbd163feca Gerrit-Change-Number: 72056 Gerrit-PatchSet: 5 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: Add missing Intel B460 flash chip id.
by Paul Menzel (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: ChrisEric1 CECL, Nicholas Chin. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72056 ) Change subject: Add missing Intel B460 flash chip id. ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/72056/comment/36c600d3_2337d33a PS4, Line 7: Add missing Intel B460 flash chip id. Nit: Please also remove the dot/period at the end [1]. [1]: https://cbea.ms/git-commit/ -- To view, visit https://review.coreboot.org/c/flashrom/+/72056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id8fcb59d5dbafea3e79c4e3ad75484bbd163feca Gerrit-Change-Number: 72056 Gerrit-PatchSet: 4 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Feb 2023 17:07:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: Add missing Intel B460 flash chip id.
by Thomas Heijligen (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: ChrisEric1 CECL, Nicholas Chin. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72056 ) Change subject: Add missing Intel B460 flash chip id. ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/72056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id8fcb59d5dbafea3e79c4e3ad75484bbd163feca Gerrit-Change-Number: 72056 Gerrit-PatchSet: 4 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Feb 2023 16:23:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in flashrom[master]: Add support for VIA VL805 USB 3 XHCI flashing
by Thomas Heijligen (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: ChrisEric1 CECL, Nicholas Chin. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72057 ) Change subject: Add support for VIA VL805 USB 3 XHCI flashing ...................................................................... Patch Set 8: (6 comments) Patchset: PS3: > Hello! […] 1. Ok, 2. Yes, thats fine. But I missed one thing. Can you add `vl805` also to `meson_options.txt` under `option('programmer', ...` 3. I'll also have a closer look for the RDID4. This has something to do with how many ID bytes were queried IIRC. I've found also an VL805 PCI card in my pile of stuff and will give your patch a try tomorrow. File flashchips.c: https://review.coreboot.org/c/flashrom/+/72057/comment/224f6d01_f91557c9 PS8, Line 19126: .probe = PROBE_SPI_RDID4, This should also be an other commit. Can be before this or after. File flashrom.8.tmpl: https://review.coreboot.org/c/flashrom/+/72057/comment/aa48f95d_248c16bd PS8, Line 1706: and raw memory access pci configutation space is enough. File vl805.c: https://review.coreboot.org/c/flashrom/+/72057/comment/472a7fc5_bb509e79 PS3, Line 38: static struct pci_dev *dev = NULL; > Cannot do that, this part is outside of the global which needs it: […] This was referred to `static struct pci_dev *dev = NULL`, not `dev_entries`. The plan is to have the `pci_dev` handle in a data struct, allocated by `vl805_init()` and passed on via the `flashxtx *ctx->mst->spi.data`. So ``` void vl805_setregval(int reg, uint32_t val) ``` becomes ``` void vl805_setregval(struct pci_dev *dev, int reg, uint32_t val) ``` And `vl805_spi_send_command` gets the pci_dev* like in `pickit2_spi.c:402` https://review.coreboot.org/c/flashrom/+/72057/comment/384dc12a_9d074372 PS3, Line 72: uint32_t indata = 0; : unsigned int curwritecnt = 0; : unsigned int curreadcnt = 0; > I don't understand what you are trying to say, if you remove the highlighted part, it fails to build […] The ` = 0` is not needed for each of them. A declaration of those variables is sufficient. They don't need to be initialized. https://review.coreboot.org/c/flashrom/+/72057/comment/125a2ad4_739206f3 PS3, Line 107: static const struct spi_master spi_master_vl805 = { > I have no clue right now, but I added it in to see if it works later. Done -- To view, visit https://review.coreboot.org/c/flashrom/+/72057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I71435afcacdf97e14d627e35bce3d29de9657f38 Gerrit-Change-Number: 72057 Gerrit-PatchSet: 8 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Feb 2023 16:18:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Comment-In-Reply-To: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: Add support for AMD Ryzen flashing
by ChrisEric1 CECL (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: Arthur Heymans, Nicholas Chin. Hello build bot (Jenkins), Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/72058 to look at the new patch set (#4). Change subject: Add support for AMD Ryzen flashing ...................................................................... Add support for AMD Ryzen flashing Tested AMD Ryzen Support on HP Pavilion 590-p0077c, I am able to flash using F.15 or older, but I can downgrade if a newer Firmware is installed using afuwinx64 which is a vendor tool This is due to flashrom SPI lockdown on newer firmwares by HP. It seems HP UEFI Diags uses AFU Flash embedded in. It also comes with a AMD Ryzen 3 2200G with 16MB, so it may not work with chips more that 16MB, it is currently untested by me, since this is the only AMD PC I own. Change-Id: Ife51f7dec31b51a7416e417112b0eedb21fae6a0 Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- M chipset_enable.c M include/flashchips.h M include/programmer.h M sb600spi.c M spi25.c 5 files changed, 41 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/58/72058/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/72058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ife51f7dec31b51a7416e417112b0eedb21fae6a0 Gerrit-Change-Number: 72058 Gerrit-PatchSet: 4 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newpatchset

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flashrom-gerrit February 2023